[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __ARM_LIB__\r
#define __ARM_LIB__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
typedef enum {\r
  ARM_CACHE_TYPE_WRITE_BACK,\r
  ARM_CACHE_TYPE_UNKNOWN\r
} ARM_CACHE_TYPE;\r
\r
typedef enum {\r
  ARM_CACHE_ARCHITECTURE_UNIFIED,\r
  ARM_CACHE_ARCHITECTURE_SEPARATE,\r
  ARM_CACHE_ARCHITECTURE_UNKNOWN\r
} ARM_CACHE_ARCHITECTURE;\r
\r
typedef struct {\r
  ARM_CACHE_TYPE          Type;\r
  ARM_CACHE_ARCHITECTURE  Architecture;\r
  BOOLEAN                 DataCachePresent;\r
  UINTN                   DataCacheSize;\r
  UINTN                   DataCacheAssociativity;\r
  UINTN                   DataCacheLineLength;\r
  BOOLEAN                 InstructionCachePresent;\r
  UINTN                   InstructionCacheSize;\r
  UINTN                   InstructionCacheAssociativity;\r
  UINTN                   InstructionCacheLineLength;\r
} ARM_CACHE_INFO;\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
ARM_CACHE_TYPE\r
EFIAPI\r
ArmCacheType (\r
  VOID\r
  );\r
\r
ARM_CACHE_ARCHITECTURE\r
EFIAPI\r
ArmCacheArchitecture (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCacheInformation (\r
  OUT ARM_CACHE_INFO  *CacheInfo\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmDataCachePresent (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheSize (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheAssociativity (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmInstructionCachePresent (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheSize (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheAssociativity (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheToPoU (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN   SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
RETURN_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,\r
  OUT VOID                         **TranslationTableBase OPTIONAL,\r
  OUT UINTN                         *TranslationTableSize  OPTIONAL\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDrainWriteBuffer (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
RETURN_STATUS\r
ArmSetMemoryRegionNoExec (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  );\r
\r
RETURN_STATUS\r
ArmClearMemoryRegionNoExec (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  );\r
\r
RETURN_STATUS\r
ArmSetMemoryRegionReadOnly (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  );\r
\r
RETURN_STATUS\r
ArmClearMemoryRegionReadOnly (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  );\r
\r
#endif // __ARM_LIB__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
90ed18ca	4	Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
1e57a462	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef __ARM_LIB__\r
	17	#define __ARM_LIB__\r
	18	\r
	19	#include <Uefi/UefiBaseType.h>\r
	20	\r
25402f5d	21	#ifdef MDE_CPU_ARM\r
70119d27	22	#include <Chipset/ArmV7.h>\r
25402f5d HL	23	#elif defined(MDE_CPU_AARCH64)\r
25402f5d HL	24	#include <Chipset/AArch64.h>\r
1e57a462	25	#else\r
25402f5d	26	#error "Unknown chipset."\r
1e57a462	27	#endif\r
	28	\r
	29	typedef enum {\r
	30	ARM_CACHE_TYPE_WRITE_BACK,\r
	31	ARM_CACHE_TYPE_UNKNOWN\r
	32	} ARM_CACHE_TYPE;\r
	33	\r
	34	typedef enum {\r
	35	ARM_CACHE_ARCHITECTURE_UNIFIED,\r
	36	ARM_CACHE_ARCHITECTURE_SEPARATE,\r
	37	ARM_CACHE_ARCHITECTURE_UNKNOWN\r
	38	} ARM_CACHE_ARCHITECTURE;\r
	39	\r
	40	typedef struct {\r
	41	ARM_CACHE_TYPE Type;\r
	42	ARM_CACHE_ARCHITECTURE Architecture;\r
	43	BOOLEAN DataCachePresent;\r
	44	UINTN DataCacheSize;\r
	45	UINTN DataCacheAssociativity;\r
	46	UINTN DataCacheLineLength;\r
	47	BOOLEAN InstructionCachePresent;\r
	48	UINTN InstructionCacheSize;\r
	49	UINTN InstructionCacheAssociativity;\r
	50	UINTN InstructionCacheLineLength;\r
	51	} ARM_CACHE_INFO;\r
	52	\r
	53	/**\r
	54	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	55	*\r
	56	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	57	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	58	*/\r
	59	typedef enum {\r
	60	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	61	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	62	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	63	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
	64	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	65	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	66	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	67	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	68	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	69	\r
	70	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	71	\r
	72	typedef struct {\r
	73	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	74	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	75	UINT64 Length;\r
1e57a462	76	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	77	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	78	\r
	79	typedef VOID (*CACHE_OPERATION)(VOID);\r
	80	typedef VOID (*LINE_OPERATION)(UINTN);\r
	81	\r
	82	//\r
	83	// ARM Processor Mode\r
	84	//\r
	85	typedef enum {\r
	86	ARM_PROCESSOR_MODE_USER = 0x10,\r
	87	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	88	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	89	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	90	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	91	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	92	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	93	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	94	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	95	} ARM_PROCESSOR_MODE;\r
	96	\r
	97	//\r
	98	// ARM Cpu IDs\r
	99	//\r
	100	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	101	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	102	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	103	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	104	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	105	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	106	\r
	107	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	108	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	109	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	110	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	111	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	112	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	113	\r
	114	//\r
	115	// ARM MP Core IDs\r
	116	//\r
90ed18ca OM	117	#define ARM_CORE_AFF0 0xFF\r
	118	#define ARM_CORE_AFF1 (0xFF << 8)\r
	119	#define ARM_CORE_AFF2 (0xFF << 16)\r
	120	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	121	\r
	122	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	123	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	124	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	125	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	126	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	127	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
	128	\r
	129	ARM_CACHE_TYPE\r
	130	EFIAPI\r
	131	ArmCacheType (\r
	132	VOID\r
	133	);\r
	134	\r
	135	ARM_CACHE_ARCHITECTURE\r
	136	EFIAPI\r
	137	ArmCacheArchitecture (\r
	138	VOID\r
	139	);\r
	140	\r
	141	VOID\r
	142	EFIAPI\r
	143	ArmCacheInformation (\r
	144	OUT ARM_CACHE_INFO *CacheInfo\r
	145	);\r
	146	\r
	147	BOOLEAN\r
	148	EFIAPI\r
	149	ArmDataCachePresent (\r
	150	VOID\r
	151	);\r
3402aac7	152	\r
1e57a462	153	UINTN\r
	154	EFIAPI\r
	155	ArmDataCacheSize (\r
	156	VOID\r
	157	);\r
3402aac7	158	\r
1e57a462	159	UINTN\r
	160	EFIAPI\r
	161	ArmDataCacheAssociativity (\r
	162	VOID\r
	163	);\r
3402aac7	164	\r
1e57a462	165	UINTN\r
	166	EFIAPI\r
	167	ArmDataCacheLineLength (\r
	168	VOID\r
	169	);\r
3402aac7	170	\r
1e57a462	171	BOOLEAN\r
	172	EFIAPI\r
	173	ArmInstructionCachePresent (\r
	174	VOID\r
	175	);\r
3402aac7	176	\r
1e57a462	177	UINTN\r
	178	EFIAPI\r
	179	ArmInstructionCacheSize (\r
	180	VOID\r
	181	);\r
3402aac7	182	\r
1e57a462	183	UINTN\r
	184	EFIAPI\r
	185	ArmInstructionCacheAssociativity (\r
	186	VOID\r
	187	);\r
3402aac7	188	\r
1e57a462	189	UINTN\r
	190	EFIAPI\r
	191	ArmInstructionCacheLineLength (\r
	192	VOID\r
	193	);\r
168d7245 OM	194	\r
	195	UINTN\r
	196	EFIAPI\r
	197	ArmIsArchTimerImplemented (\r
	198	VOID\r
	199	);\r
	200	\r
	201	UINTN\r
	202	EFIAPI\r
	203	ArmReadIdPfr0 (\r
	204	VOID\r
	205	);\r
	206	\r
	207	UINTN\r
	208	EFIAPI\r
	209	ArmReadIdPfr1 (\r
	210	VOID\r
	211	);\r
	212	\r
64751727	213	UINTN\r
1e57a462	214	EFIAPI\r
64751727	215	ArmCacheInfo (\r
1e57a462	216	VOID\r
	217	);\r
	218	\r
	219	BOOLEAN\r
	220	EFIAPI\r
	221	ArmIsMpCore (\r
	222	VOID\r
	223	);\r
	224	\r
	225	VOID\r
	226	EFIAPI\r
	227	ArmInvalidateDataCache (\r
	228	VOID\r
	229	);\r
	230	\r
	231	\r
	232	VOID\r
	233	EFIAPI\r
	234	ArmCleanInvalidateDataCache (\r
	235	VOID\r
	236	);\r
	237	\r
	238	VOID\r
	239	EFIAPI\r
	240	ArmCleanDataCache (\r
	241	VOID\r
	242	);\r
	243	\r
	244	VOID\r
	245	EFIAPI\r
	246	ArmCleanDataCacheToPoU (\r
	247	VOID\r
	248	);\r
	249	\r
	250	VOID\r
	251	EFIAPI\r
	252	ArmInvalidateInstructionCache (\r
	253	VOID\r
	254	);\r
	255	\r
	256	VOID\r
	257	EFIAPI\r
	258	ArmInvalidateDataCacheEntryByMVA (\r
	259	IN UINTN Address\r
	260	);\r
	261	\r
	262	VOID\r
	263	EFIAPI\r
	264	ArmCleanDataCacheEntryByMVA (\r
	265	IN UINTN Address\r
	266	);\r
	267	\r
	268	VOID\r
	269	EFIAPI\r
	270	ArmCleanInvalidateDataCacheEntryByMVA (\r
	271	IN UINTN Address\r
	272	);\r
	273	\r
0ff0e414 OM	274	VOID\r
	275	EFIAPI\r
	276	ArmInvalidateDataCacheEntryBySetWay (\r
	277	IN UINTN SetWayFormat\r
	278	);\r
	279	\r
	280	VOID\r
	281	EFIAPI\r
	282	ArmCleanDataCacheEntryBySetWay (\r
	283	IN UINTN SetWayFormat\r
	284	);\r
	285	\r
	286	VOID\r
	287	EFIAPI\r
	288	ArmCleanInvalidateDataCacheEntryBySetWay (\r
	289	IN UINTN SetWayFormat\r
	290	);\r
	291	\r
1e57a462	292	VOID\r
	293	EFIAPI\r
	294	ArmEnableDataCache (\r
	295	VOID\r
	296	);\r
	297	\r
	298	VOID\r
	299	EFIAPI\r
	300	ArmDisableDataCache (\r
	301	VOID\r
	302	);\r
	303	\r
	304	VOID\r
	305	EFIAPI\r
	306	ArmEnableInstructionCache (\r
	307	VOID\r
	308	);\r
	309	\r
	310	VOID\r
	311	EFIAPI\r
	312	ArmDisableInstructionCache (\r
	313	VOID\r
	314	);\r
3402aac7	315	\r
1e57a462	316	VOID\r
	317	EFIAPI\r
	318	ArmEnableMmu (\r
	319	VOID\r
	320	);\r
	321	\r
	322	VOID\r
	323	EFIAPI\r
	324	ArmDisableMmu (\r
	325	VOID\r
	326	);\r
	327	\r
0ff0e414 OM	328	VOID\r
	329	EFIAPI\r
	330	ArmEnableCachesAndMmu (\r
	331	VOID\r
	332	);\r
	333	\r
1e57a462	334	VOID\r
	335	EFIAPI\r
	336	ArmDisableCachesAndMmu (\r
	337	VOID\r
	338	);\r
	339	\r
1e57a462	340	VOID\r
	341	EFIAPI\r
	342	ArmEnableInterrupts (\r
	343	VOID\r
	344	);\r
	345	\r
	346	UINTN\r
	347	EFIAPI\r
	348	ArmDisableInterrupts (\r
	349	VOID\r
	350	);\r
47585ed5	351	\r
1e57a462	352	BOOLEAN\r
	353	EFIAPI\r
	354	ArmGetInterruptState (\r
	355	VOID\r
	356	);\r
	357	\r
0ff0e414 OM	358	VOID\r
	359	EFIAPI\r
	360	ArmEnableAsynchronousAbort (\r
	361	VOID\r
	362	);\r
	363	\r
47585ed5	364	UINTN\r
47585ed5	365	EFIAPI\r
0ff0e414	366	ArmDisableAsynchronousAbort (\r
47585ed5	367	VOID\r
	368	);\r
	369	\r
	370	VOID\r
	371	EFIAPI\r
	372	ArmEnableIrq (\r
	373	VOID\r
	374	);\r
	375	\r
0ff0e414 OM	376	UINTN\r
	377	EFIAPI\r
	378	ArmDisableIrq (\r
	379	VOID\r
	380	);\r
	381	\r
1e57a462	382	VOID\r
	383	EFIAPI\r
	384	ArmEnableFiq (\r
	385	VOID\r
	386	);\r
	387	\r
	388	UINTN\r
	389	EFIAPI\r
	390	ArmDisableFiq (\r
	391	VOID\r
	392	);\r
3402aac7	393	\r
1e57a462	394	BOOLEAN\r
	395	EFIAPI\r
	396	ArmGetFiqState (\r
	397	VOID\r
	398	);\r
	399	\r
8dd618d2 OM	400	/**\r
	401	* Invalidate Data and Instruction TLBs\r
	402	*/\r
1e57a462	403	VOID\r
	404	EFIAPI\r
	405	ArmInvalidateTlb (\r
	406	VOID\r
	407	);\r
3402aac7	408	\r
1e57a462	409	VOID\r
	410	EFIAPI\r
	411	ArmUpdateTranslationTableEntry (\r
	412	IN VOID *TranslationTableEntry,\r
	413	IN VOID *Mva\r
	414	);\r
3402aac7	415	\r
1e57a462	416	VOID\r
	417	EFIAPI\r
	418	ArmSetDomainAccessControl (\r
	419	IN UINT32 Domain\r
	420	);\r
	421	\r
	422	VOID\r
	423	EFIAPI\r
	424	ArmSetTTBR0 (\r
	425	IN VOID *TranslationTableBase\r
	426	);\r
	427	\r
	428	VOID *\r
	429	EFIAPI\r
	430	ArmGetTTBR0BaseAddress (\r
	431	VOID\r
	432	);\r
	433	\r
6f050ad6	434	RETURN_STATUS\r
1e57a462	435	EFIAPI\r
	436	ArmConfigureMmu (\r
	437	IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
6f050ad6	438	OUT VOID **TranslationTableBase OPTIONAL,\r
1e57a462	439	OUT UINTN *TranslationTableSize OPTIONAL\r
1e57a462	440	);\r
3402aac7	441	\r
1e57a462	442	BOOLEAN\r
	443	EFIAPI\r
	444	ArmMmuEnabled (\r
	445	VOID\r
	446	);\r
3402aac7	447	\r
1e57a462	448	VOID\r
	449	EFIAPI\r
	450	ArmEnableBranchPrediction (\r
	451	VOID\r
	452	);\r
	453	\r
	454	VOID\r
	455	EFIAPI\r
	456	ArmDisableBranchPrediction (\r
	457	VOID\r
	458	);\r
	459	\r
	460	VOID\r
	461	EFIAPI\r
	462	ArmSetLowVectors (\r
	463	VOID\r
	464	);\r
	465	\r
	466	VOID\r
	467	EFIAPI\r
	468	ArmSetHighVectors (\r
	469	VOID\r
	470	);\r
	471	\r
0ff0e414 OM	472	VOID\r
	473	EFIAPI\r
	474	ArmDrainWriteBuffer (\r
	475	VOID\r
	476	);\r
	477	\r
1e57a462	478	VOID\r
	479	EFIAPI\r
	480	ArmDataMemoryBarrier (\r
	481	VOID\r
	482	);\r
3402aac7	483	\r
1e57a462	484	VOID\r
1e57a462	485	EFIAPI\r
cf93a378	486	ArmDataSynchronizationBarrier (\r
1e57a462	487	VOID\r
1e57a462	488	);\r
3402aac7	489	\r
1e57a462	490	VOID\r
	491	EFIAPI\r
	492	ArmInstructionSynchronizationBarrier (\r
	493	VOID\r
	494	);\r
	495	\r
	496	VOID\r
	497	EFIAPI\r
	498	ArmWriteVBar (\r
4e57d6d7	499	IN UINTN VectorBase\r
1e57a462	500	);\r
1e57a462	501	\r
4e57d6d7	502	UINTN\r
1e57a462	503	EFIAPI\r
	504	ArmReadVBar (\r
	505	VOID\r
	506	);\r
	507	\r
	508	VOID\r
	509	EFIAPI\r
	510	ArmWriteAuxCr (\r
	511	IN UINT32 Bit\r
	512	);\r
	513	\r
	514	UINT32\r
	515	EFIAPI\r
	516	ArmReadAuxCr (\r
	517	VOID\r
	518	);\r
	519	\r
	520	VOID\r
	521	EFIAPI\r
	522	ArmSetAuxCrBit (\r
	523	IN UINT32 Bits\r
	524	);\r
	525	\r
	526	VOID\r
	527	EFIAPI\r
	528	ArmUnsetAuxCrBit (\r
	529	IN UINT32 Bits\r
	530	);\r
	531	\r
	532	VOID\r
	533	EFIAPI\r
	534	ArmCallSEV (\r
	535	VOID\r
	536	);\r
	537	\r
	538	VOID\r
	539	EFIAPI\r
	540	ArmCallWFE (\r
	541	VOID\r
	542	);\r
	543	\r
	544	VOID\r
	545	EFIAPI\r
	546	ArmCallWFI (\r
25402f5d	547	\r
1e57a462	548	VOID\r
	549	);\r
	550	\r
	551	UINTN\r
	552	EFIAPI\r
	553	ArmReadMpidr (\r
	554	VOID\r
	555	);\r
	556	\r
9401d6f4 OM	557	UINTN\r
	558	EFIAPI\r
	559	ArmReadMidr (\r
	560	VOID\r
	561	);\r
	562	\r
1e57a462	563	UINT32\r
	564	EFIAPI\r
	565	ArmReadCpacr (\r
	566	VOID\r
	567	);\r
	568	\r
	569	VOID\r
	570	EFIAPI\r
	571	ArmWriteCpacr (\r
	572	IN UINT32 Access\r
	573	);\r
	574	\r
	575	VOID\r
	576	EFIAPI\r
	577	ArmEnableVFP (\r
	578	VOID\r
	579	);\r
	580	\r
46d4d75c OM	581	/**\r
	582	Get the Secure Configuration Register value\r
	583	\r
	584	@return Value read from the Secure Configuration Register\r
	585	\r
	586	**/\r
1e57a462	587	UINT32\r
	588	EFIAPI\r
	589	ArmReadScr (\r
	590	VOID\r
	591	);\r
	592	\r
46d4d75c OM	593	/**\r
	594	Set the Secure Configuration Register\r
	595	\r
	596	@param Value Value to write to the Secure Configuration Register\r
	597	\r
	598	**/\r
1e57a462	599	VOID\r
	600	EFIAPI\r
	601	ArmWriteScr (\r
46d4d75c	602	IN UINT32 Value\r
1e57a462	603	);\r
	604	\r
	605	UINT32\r
	606	EFIAPI\r
	607	ArmReadMVBar (\r
	608	VOID\r
	609	);\r
	610	\r
	611	VOID\r
	612	EFIAPI\r
	613	ArmWriteMVBar (\r
	614	IN UINT32 VectorMonitorBase\r
	615	);\r
	616	\r
	617	UINT32\r
	618	EFIAPI\r
	619	ArmReadSctlr (\r
	620	VOID\r
	621	);\r
	622	\r
5ea2c2d3	623	UINTN\r
	624	EFIAPI\r
	625	ArmReadHVBar (\r
	626	VOID\r
	627	);\r
	628	\r
	629	VOID\r
	630	EFIAPI\r
	631	ArmWriteHVBar (\r
	632	IN UINTN HypModeVectorBase\r
	633	);\r
	634	\r
52d44f77 OM	635	\r
	636	//\r
	637	// Helper functions for accessing CPU ACTLR\r
	638	//\r
	639	\r
	640	UINTN\r
	641	EFIAPI\r
	642	ArmReadCpuActlr (\r
	643	VOID\r
	644	);\r
	645	\r
	646	VOID\r
	647	EFIAPI\r
	648	ArmWriteCpuActlr (\r
	649	IN UINTN Val\r
	650	);\r
	651	\r
	652	VOID\r
	653	EFIAPI\r
	654	ArmSetCpuActlrBit (\r
	655	IN UINTN Bits\r
	656	);\r
	657	\r
	658	VOID\r
	659	EFIAPI\r
	660	ArmUnsetCpuActlrBit (\r
	661	IN UINTN Bits\r
	662	);\r
	663	\r
4d9a4f62 AB	664	RETURN_STATUS\r
	665	ArmSetMemoryRegionNoExec (\r
	666	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	667	IN UINT64 Length\r
	668	);\r
	669	\r
	670	RETURN_STATUS\r
	671	ArmClearMemoryRegionNoExec (\r
	672	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	673	IN UINT64 Length\r
	674	);\r
	675	\r
	676	RETURN_STATUS\r
	677	ArmSetMemoryRegionReadOnly (\r
	678	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	679	IN UINT64 Length\r
	680	);\r
	681	\r
	682	RETURN_STATUS\r
	683	ArmClearMemoryRegionReadOnly (\r
	684	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	685	IN UINT64 Length\r
	686	);\r
	687	\r
1e57a462	688	#endif // __ARM_LIB__\r