Updating ArmLib.h to add functions needed to turn on paging in CpuDxe. Also added...
[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h
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1/** @file
2
3 Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
4
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15#ifndef __ARM_LIB__
16#define __ARM_LIB__
17
18typedef enum {
19 ARM_CACHE_TYPE_WRITE_BACK,
20 ARM_CACHE_TYPE_UNKNOWN
21} ARM_CACHE_TYPE;
22
23typedef enum {
24 ARM_CACHE_ARCHITECTURE_UNIFIED,
25 ARM_CACHE_ARCHITECTURE_SEPARATE,
26 ARM_CACHE_ARCHITECTURE_UNKNOWN
27} ARM_CACHE_ARCHITECTURE;
28
29typedef struct {
30 ARM_CACHE_TYPE Type;
31 ARM_CACHE_ARCHITECTURE Architecture;
32 BOOLEAN DataCachePresent;
33 UINTN DataCacheSize;
34 UINTN DataCacheAssociativity;
35 UINTN DataCacheLineLength;
36 BOOLEAN InstructionCachePresent;
37 UINTN InstructionCacheSize;
38 UINTN InstructionCacheAssociativity;
39 UINTN InstructionCacheLineLength;
40} ARM_CACHE_INFO;
41
42typedef enum {
43 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED,
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
45 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
46 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
47} ARM_MEMORY_REGION_ATTRIBUTES;
48
49typedef struct {
50 UINT32 PhysicalBase;
51 UINT32 VirtualBase;
52 UINT32 Length;
53 ARM_MEMORY_REGION_ATTRIBUTES Attributes;
54} ARM_MEMORY_REGION_DESCRIPTOR;
55
56typedef VOID (*CACHE_OPERATION)(VOID);
57typedef VOID (*LINE_OPERATION)(UINTN);
58
59typedef enum {
60 ARM_PROCESSOR_MODE_USER = 0x10,
61 ARM_PROCESSOR_MODE_FIQ = 0x11,
62 ARM_PROCESSOR_MODE_IRQ = 0x12,
63 ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
64 ARM_PROCESSOR_MODE_ABORT = 0x17,
65 ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
66 ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
67 ARM_PROCESSOR_MODE_MASK = 0x1F
68} ARM_PROCESSOR_MODE;
69
70ARM_CACHE_TYPE
71EFIAPI
72ArmCacheType (
73 VOID
74 );
75
76ARM_CACHE_ARCHITECTURE
77EFIAPI
78ArmCacheArchitecture (
79 VOID
80 );
81
82VOID
83EFIAPI
84ArmCacheInformation (
85 OUT ARM_CACHE_INFO *CacheInfo
86 );
87
88BOOLEAN
89EFIAPI
90ArmDataCachePresent (
91 VOID
92 );
93
94UINTN
95EFIAPI
96ArmDataCacheSize (
97 VOID
98 );
99
100UINTN
101EFIAPI
102ArmDataCacheAssociativity (
103 VOID
104 );
105
106UINTN
107EFIAPI
108ArmDataCacheLineLength (
109 VOID
110 );
111
112BOOLEAN
113EFIAPI
114ArmInstructionCachePresent (
115 VOID
116 );
117
118UINTN
119EFIAPI
120ArmInstructionCacheSize (
121 VOID
122 );
123
124UINTN
125EFIAPI
126ArmInstructionCacheAssociativity (
127 VOID
128 );
129
130UINTN
131EFIAPI
132ArmInstructionCacheLineLength (
133 VOID
134 );
135
136UINT32
137EFIAPI
138Cp15IdCode (
139 VOID
140 );
141
142UINT32
143EFIAPI
144Cp15CacheInfo (
145 VOID
146 );
147
148VOID
149EFIAPI
150ArmInvalidateDataCache (
151 VOID
152 );
153
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155VOID
156EFIAPI
157ArmCleanInvalidateDataCache (
158 VOID
159 );
160
161VOID
162EFIAPI
163ArmCleanDataCache (
164 VOID
165 );
166
167VOID
168EFIAPI
169ArmInvalidateInstructionCache (
170 VOID
171 );
172
173VOID
174EFIAPI
175ArmInvalidateDataCacheEntryByMVA (
176 IN UINTN Address
177 );
178
179VOID
180EFIAPI
181ArmCleanDataCacheEntryByMVA (
182 IN UINTN Address
183 );
184
185VOID
186EFIAPI
187ArmCleanInvalidateDataCacheEntryByMVA (
188 IN UINTN Address
189 );
190
191VOID
192EFIAPI
193ArmEnableDataCache (
194 VOID
195 );
196
197VOID
198EFIAPI
199ArmDisableDataCache (
200 VOID
201 );
202
203VOID
204EFIAPI
205ArmEnableInstructionCache (
206 VOID
207 );
208
209VOID
210EFIAPI
211ArmDisableInstructionCache (
212 VOID
213 );
214
215VOID
216EFIAPI
217ArmEnableMmu (
218 VOID
219 );
220
221VOID
222EFIAPI
223ArmDisableMmu (
224 VOID
225 );
226
227VOID
228EFIAPI
229ArmEnableInterrupts (
230 VOID
231 );
232
233UINTN
234EFIAPI
235ArmDisableInterrupts (
236 VOID
237 );
238
239BOOLEAN
240EFIAPI
241ArmGetInterruptState (
242 VOID
243 );
244
245VOID
246EFIAPI
247ArmInvalidateTlb (
248 VOID
249 );
250
251VOID
252EFIAPI
253ArmSetDomainAccessControl (
254 IN UINT32 Domain
255 );
256
257VOID
258EFIAPI
259ArmSetTranslationTableBaseAddress (
260 IN VOID *TranslationTableBase
261 );
262
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263VOID *
264EFIAPI
265ArmGetTranslationTableBaseAddress (
266 );
267
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268VOID
269EFIAPI
270ArmConfigureMmu (
271 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
272 OUT VOID **TranslationTableBase OPTIONAL,
273 OUT UINTN *TranslationTableSize OPTIONAL
274 );
275
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276BOOLEAN
277EFIAPI
278ArmMmuEnabled (
279 VOID
280 );
281
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282VOID
283EFIAPI
284ArmSwitchProcessorMode (
285 IN ARM_PROCESSOR_MODE Mode
286 );
287
288ARM_PROCESSOR_MODE
289EFIAPI
290ArmProcessorMode (
291 VOID
292 );
293
294VOID
295EFIAPI
296ArmEnableBranchPrediction (
297 VOID
298 );
299
300VOID
301EFIAPI
302ArmDisableBranchPrediction (
303 VOID
304 );
305
306#endif // __ARM_LIB__