Commit | Line | Data |
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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
15f5b04e | 4 | Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.\r |
3402aac7 | 5 | \r |
4059386c | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1e57a462 | 7 | \r |
8 | **/\r | |
9 | #include <Base.h>\r | |
10 | #include <Library/ArmLib.h>\r | |
f977e650 | 11 | #include <Library/DebugLib.h>\r |
1e57a462 | 12 | #include <Library/PcdLib.h>\r |
13 | \r | |
cf580da1 | 14 | STATIC\r |
1e57a462 | 15 | VOID\r |
16 | CacheRangeOperation (\r | |
17 | IN VOID *Start,\r | |
18 | IN UINTN Length,\r | |
cf580da1 AB |
19 | IN LINE_OPERATION LineOperation,\r |
20 | IN UINTN LineLength\r | |
1e57a462 | 21 | )\r |
22 | {\r | |
429309e0 | 23 | UINTN ArmCacheLineAlignmentMask;\r |
6ea34e3a | 24 | // Align address (rounding down)\r |
429309e0 MK |
25 | UINTN AlignedAddress;\r |
26 | UINTN EndAddress;\r | |
15f5b04e PG |
27 | \r |
28 | ArmCacheLineAlignmentMask = LineLength - 1;\r | |
429309e0 MK |
29 | AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r |
30 | EndAddress = (UINTN)Start + Length;\r | |
1e57a462 | 31 | \r |
6ea34e3a AB |
32 | // Perform the line operation on an address in each cache line\r |
33 | while (AlignedAddress < EndAddress) {\r | |
429309e0 | 34 | LineOperation (AlignedAddress);\r |
cf580da1 | 35 | AlignedAddress += LineLength;\r |
1e57a462 | 36 | }\r |
429309e0 | 37 | \r |
c7222893 | 38 | ArmDataSynchronizationBarrier ();\r |
1e57a462 | 39 | }\r |
40 | \r | |
41 | VOID\r | |
42 | EFIAPI\r | |
43 | InvalidateInstructionCache (\r | |
44 | VOID\r | |
45 | )\r | |
46 | {\r | |
ce6aec3e | 47 | ASSERT (FALSE);\r |
1e57a462 | 48 | }\r |
49 | \r | |
50 | VOID\r | |
51 | EFIAPI\r | |
52 | InvalidateDataCache (\r | |
53 | VOID\r | |
54 | )\r | |
55 | {\r | |
f977e650 | 56 | ASSERT (FALSE);\r |
1e57a462 | 57 | }\r |
58 | \r | |
59 | VOID *\r | |
60 | EFIAPI\r | |
61 | InvalidateInstructionCacheRange (\r | |
429309e0 MK |
62 | IN VOID *Address,\r |
63 | IN UINTN Length\r | |
1e57a462 | 64 | )\r |
65 | {\r | |
429309e0 MK |
66 | CacheRangeOperation (\r |
67 | Address,\r | |
68 | Length,\r | |
69 | ArmCleanDataCacheEntryToPoUByMVA,\r | |
70 | ArmDataCacheLineLength ()\r | |
71 | );\r | |
72 | CacheRangeOperation (\r | |
73 | Address,\r | |
74 | Length,\r | |
cf580da1 | 75 | ArmInvalidateInstructionCacheEntryToPoUByMVA,\r |
429309e0 MK |
76 | ArmInstructionCacheLineLength ()\r |
77 | );\r | |
cf580da1 AB |
78 | \r |
79 | ArmInstructionSynchronizationBarrier ();\r | |
80 | \r | |
1e57a462 | 81 | return Address;\r |
82 | }\r | |
83 | \r | |
84 | VOID\r | |
85 | EFIAPI\r | |
86 | WriteBackInvalidateDataCache (\r | |
87 | VOID\r | |
88 | )\r | |
89 | {\r | |
f977e650 | 90 | ASSERT (FALSE);\r |
1e57a462 | 91 | }\r |
92 | \r | |
93 | VOID *\r | |
94 | EFIAPI\r | |
95 | WriteBackInvalidateDataCacheRange (\r | |
429309e0 MK |
96 | IN VOID *Address,\r |
97 | IN UINTN Length\r | |
1e57a462 | 98 | )\r |
99 | {\r | |
429309e0 MK |
100 | CacheRangeOperation (\r |
101 | Address,\r | |
102 | Length,\r | |
103 | ArmCleanInvalidateDataCacheEntryByMVA,\r | |
104 | ArmDataCacheLineLength ()\r | |
105 | );\r | |
1e57a462 | 106 | return Address;\r |
107 | }\r | |
108 | \r | |
109 | VOID\r | |
110 | EFIAPI\r | |
111 | WriteBackDataCache (\r | |
112 | VOID\r | |
113 | )\r | |
114 | {\r | |
f977e650 | 115 | ASSERT (FALSE);\r |
1e57a462 | 116 | }\r |
117 | \r | |
118 | VOID *\r | |
119 | EFIAPI\r | |
120 | WriteBackDataCacheRange (\r | |
429309e0 MK |
121 | IN VOID *Address,\r |
122 | IN UINTN Length\r | |
1e57a462 | 123 | )\r |
124 | {\r | |
429309e0 MK |
125 | CacheRangeOperation (\r |
126 | Address,\r | |
127 | Length,\r | |
128 | ArmCleanDataCacheEntryByMVA,\r | |
129 | ArmDataCacheLineLength ()\r | |
130 | );\r | |
1e57a462 | 131 | return Address;\r |
132 | }\r | |
133 | \r | |
134 | VOID *\r | |
135 | EFIAPI\r | |
136 | InvalidateDataCacheRange (\r | |
429309e0 MK |
137 | IN VOID *Address,\r |
138 | IN UINTN Length\r | |
1e57a462 | 139 | )\r |
140 | {\r | |
429309e0 MK |
141 | CacheRangeOperation (\r |
142 | Address,\r | |
143 | Length,\r | |
144 | ArmInvalidateDataCacheEntryByMVA,\r | |
145 | ArmDataCacheLineLength ()\r | |
146 | );\r | |
1e57a462 | 147 | return Address;\r |
148 | }\r |