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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
01674afd | 4 | Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
1e57a462 | 5 | \r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/ArmLib.h>\r | |
17 | #include <Library/PcdLib.h>\r | |
18 | \r | |
19 | VOID\r | |
20 | CacheRangeOperation (\r | |
21 | IN VOID *Start,\r | |
22 | IN UINTN Length,\r | |
23 | IN CACHE_OPERATION CacheOperation,\r | |
24 | IN LINE_OPERATION LineOperation\r | |
25 | )\r | |
26 | {\r | |
27 | UINTN ArmCacheLineLength = ArmDataCacheLineLength();\r | |
28 | UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;\r | |
29 | UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);\r | |
30 | \r | |
31 | if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {\r | |
01674afd | 32 | ArmDrainWriteBuffer ();\r |
1e57a462 | 33 | CacheOperation ();\r |
34 | } else {\r | |
35 | // Align address (rounding down)\r | |
36 | UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r | |
37 | UINTN EndAddress = (UINTN)Start + Length;\r | |
38 | \r | |
39 | // Perform the line operation on an address in each cache line\r | |
40 | while (AlignedAddress < EndAddress) {\r | |
41 | LineOperation(AlignedAddress);\r | |
42 | AlignedAddress += ArmCacheLineLength;\r | |
43 | }\r | |
44 | }\r | |
45 | }\r | |
46 | \r | |
47 | VOID\r | |
48 | EFIAPI\r | |
49 | InvalidateInstructionCache (\r | |
50 | VOID\r | |
51 | )\r | |
52 | {\r | |
53 | ArmCleanDataCache();\r | |
54 | ArmInvalidateInstructionCache();\r | |
55 | }\r | |
56 | \r | |
57 | VOID\r | |
58 | EFIAPI\r | |
59 | InvalidateDataCache (\r | |
60 | VOID\r | |
61 | )\r | |
62 | {\r | |
63 | ArmInvalidateDataCache();\r | |
64 | }\r | |
65 | \r | |
66 | VOID *\r | |
67 | EFIAPI\r | |
68 | InvalidateInstructionCacheRange (\r | |
69 | IN VOID *Address,\r | |
70 | IN UINTN Length\r | |
71 | )\r | |
72 | {\r | |
73 | CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);\r | |
74 | ArmInvalidateInstructionCache ();\r | |
75 | return Address;\r | |
76 | }\r | |
77 | \r | |
78 | VOID\r | |
79 | EFIAPI\r | |
80 | WriteBackInvalidateDataCache (\r | |
81 | VOID\r | |
82 | )\r | |
83 | {\r | |
84 | ArmCleanInvalidateDataCache();\r | |
85 | }\r | |
86 | \r | |
87 | VOID *\r | |
88 | EFIAPI\r | |
89 | WriteBackInvalidateDataCacheRange (\r | |
90 | IN VOID *Address,\r | |
91 | IN UINTN Length\r | |
92 | )\r | |
93 | {\r | |
94 | CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);\r | |
95 | return Address;\r | |
96 | }\r | |
97 | \r | |
98 | VOID\r | |
99 | EFIAPI\r | |
100 | WriteBackDataCache (\r | |
101 | VOID\r | |
102 | )\r | |
103 | {\r | |
104 | ArmCleanDataCache();\r | |
105 | }\r | |
106 | \r | |
107 | VOID *\r | |
108 | EFIAPI\r | |
109 | WriteBackDataCacheRange (\r | |
110 | IN VOID *Address,\r | |
111 | IN UINTN Length\r | |
112 | )\r | |
113 | {\r | |
114 | CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);\r | |
115 | return Address;\r | |
116 | }\r | |
117 | \r | |
118 | VOID *\r | |
119 | EFIAPI\r | |
120 | InvalidateDataCacheRange (\r | |
121 | IN VOID *Address,\r | |
122 | IN UINTN Length\r | |
123 | )\r | |
124 | {\r | |
125 | CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);\r | |
126 | return Address;\r | |
127 | }\r |