]>
Commit | Line | Data |
---|---|---|
1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | #include <Base.h>\r | |
15 | #include <Library/ArmLib.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | \r | |
18 | VOID\r | |
19 | CacheRangeOperation (\r | |
20 | IN VOID *Start,\r | |
21 | IN UINTN Length,\r | |
22 | IN CACHE_OPERATION CacheOperation,\r | |
23 | IN LINE_OPERATION LineOperation\r | |
24 | )\r | |
25 | {\r | |
26 | UINTN ArmCacheLineLength = ArmDataCacheLineLength();\r | |
27 | UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;\r | |
28 | UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);\r | |
29 | \r | |
30 | if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {\r | |
31 | CacheOperation ();\r | |
32 | } else {\r | |
33 | // Align address (rounding down)\r | |
34 | UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r | |
35 | UINTN EndAddress = (UINTN)Start + Length;\r | |
36 | \r | |
37 | // Perform the line operation on an address in each cache line\r | |
38 | while (AlignedAddress < EndAddress) {\r | |
39 | LineOperation(AlignedAddress);\r | |
40 | AlignedAddress += ArmCacheLineLength;\r | |
41 | }\r | |
42 | }\r | |
43 | }\r | |
44 | \r | |
45 | VOID\r | |
46 | EFIAPI\r | |
47 | InvalidateInstructionCache (\r | |
48 | VOID\r | |
49 | )\r | |
50 | {\r | |
51 | ArmCleanDataCache();\r | |
52 | ArmInvalidateInstructionCache();\r | |
53 | }\r | |
54 | \r | |
55 | VOID\r | |
56 | EFIAPI\r | |
57 | InvalidateDataCache (\r | |
58 | VOID\r | |
59 | )\r | |
60 | {\r | |
61 | ArmInvalidateDataCache();\r | |
62 | }\r | |
63 | \r | |
64 | VOID *\r | |
65 | EFIAPI\r | |
66 | InvalidateInstructionCacheRange (\r | |
67 | IN VOID *Address,\r | |
68 | IN UINTN Length\r | |
69 | )\r | |
70 | {\r | |
71 | CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);\r | |
72 | ArmInvalidateInstructionCache ();\r | |
73 | return Address;\r | |
74 | }\r | |
75 | \r | |
76 | VOID\r | |
77 | EFIAPI\r | |
78 | WriteBackInvalidateDataCache (\r | |
79 | VOID\r | |
80 | )\r | |
81 | {\r | |
82 | ArmCleanInvalidateDataCache();\r | |
83 | }\r | |
84 | \r | |
85 | VOID *\r | |
86 | EFIAPI\r | |
87 | WriteBackInvalidateDataCacheRange (\r | |
88 | IN VOID *Address,\r | |
89 | IN UINTN Length\r | |
90 | )\r | |
91 | {\r | |
92 | CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);\r | |
93 | return Address;\r | |
94 | }\r | |
95 | \r | |
96 | VOID\r | |
97 | EFIAPI\r | |
98 | WriteBackDataCache (\r | |
99 | VOID\r | |
100 | )\r | |
101 | {\r | |
102 | ArmCleanDataCache();\r | |
103 | }\r | |
104 | \r | |
105 | VOID *\r | |
106 | EFIAPI\r | |
107 | WriteBackDataCacheRange (\r | |
108 | IN VOID *Address,\r | |
109 | IN UINTN Length\r | |
110 | )\r | |
111 | {\r | |
112 | CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);\r | |
113 | return Address;\r | |
114 | }\r | |
115 | \r | |
116 | VOID *\r | |
117 | EFIAPI\r | |
118 | InvalidateDataCacheRange (\r | |
119 | IN VOID *Address,\r | |
120 | IN UINTN Length\r | |
121 | )\r | |
122 | {\r | |
123 | CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);\r | |
124 | return Address;\r | |
125 | }\r |