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UefiCpuPkg: Change complex DEBUG_CODE() to DEBUG_CODE_BEGIN/END()
[mirror_edk2.git] / ArmPkg / Library / ArmCacheMaintenanceLib / ArmCacheMaintenanceLib.c
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1e57a462 1/** @file\r
2\r
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
15f5b04e 4 Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.\r
3402aac7 5\r
4059386c 6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
1e57a462 7\r
8**/\r
9#include <Base.h>\r
10#include <Library/ArmLib.h>\r
f977e650 11#include <Library/DebugLib.h>\r
1e57a462 12#include <Library/PcdLib.h>\r
13\r
cf580da1 14STATIC\r
1e57a462 15VOID\r
16CacheRangeOperation (\r
17 IN VOID *Start,\r
18 IN UINTN Length,\r
cf580da1
AB
19 IN LINE_OPERATION LineOperation,\r
20 IN UINTN LineLength\r
1e57a462 21 )\r
22{\r
15f5b04e 23 UINTN ArmCacheLineAlignmentMask;\r
6ea34e3a 24 // Align address (rounding down)\r
15f5b04e
PG
25 UINTN AlignedAddress;\r
26 UINTN EndAddress;\r
27\r
28 ArmCacheLineAlignmentMask = LineLength - 1;\r
29 AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r
30 EndAddress = (UINTN)Start + Length;\r
1e57a462 31\r
6ea34e3a
AB
32 // Perform the line operation on an address in each cache line\r
33 while (AlignedAddress < EndAddress) {\r
34 LineOperation(AlignedAddress);\r
cf580da1 35 AlignedAddress += LineLength;\r
1e57a462 36 }\r
c7222893 37 ArmDataSynchronizationBarrier ();\r
1e57a462 38}\r
39\r
40VOID\r
41EFIAPI\r
42InvalidateInstructionCache (\r
43 VOID\r
44 )\r
45{\r
ce6aec3e 46 ASSERT (FALSE);\r
1e57a462 47}\r
48\r
49VOID\r
50EFIAPI\r
51InvalidateDataCache (\r
52 VOID\r
53 )\r
54{\r
f977e650 55 ASSERT (FALSE);\r
1e57a462 56}\r
57\r
58VOID *\r
59EFIAPI\r
60InvalidateInstructionCacheRange (\r
61 IN VOID *Address,\r
62 IN UINTN Length\r
63 )\r
64{\r
cf580da1
AB
65 CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,\r
66 ArmDataCacheLineLength ());\r
67 CacheRangeOperation (Address, Length,\r
68 ArmInvalidateInstructionCacheEntryToPoUByMVA,\r
69 ArmInstructionCacheLineLength ());\r
70\r
71 ArmInstructionSynchronizationBarrier ();\r
72\r
1e57a462 73 return Address;\r
74}\r
75\r
76VOID\r
77EFIAPI\r
78WriteBackInvalidateDataCache (\r
79 VOID\r
80 )\r
81{\r
f977e650 82 ASSERT (FALSE);\r
1e57a462 83}\r
84\r
85VOID *\r
86EFIAPI\r
87WriteBackInvalidateDataCacheRange (\r
88 IN VOID *Address,\r
89 IN UINTN Length\r
90 )\r
91{\r
cf580da1
AB
92 CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,\r
93 ArmDataCacheLineLength ());\r
1e57a462 94 return Address;\r
95}\r
96\r
97VOID\r
98EFIAPI\r
99WriteBackDataCache (\r
100 VOID\r
101 )\r
102{\r
f977e650 103 ASSERT (FALSE);\r
1e57a462 104}\r
105\r
106VOID *\r
107EFIAPI\r
108WriteBackDataCacheRange (\r
109 IN VOID *Address,\r
110 IN UINTN Length\r
111 )\r
112{\r
cf580da1
AB
113 CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,\r
114 ArmDataCacheLineLength ());\r
1e57a462 115 return Address;\r
116}\r
117\r
118VOID *\r
119EFIAPI\r
120InvalidateDataCacheRange (\r
121 IN VOID *Address,\r
122 IN UINTN Length\r
123 )\r
124{\r
cf580da1
AB
125 CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,\r
126 ArmDataCacheLineLength ());\r
1e57a462 127 return Address;\r
128}\r