Commit | Line | Data |
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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
01674afd | 4 | Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
3402aac7 | 5 | \r |
4059386c | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1e57a462 | 7 | \r |
8 | **/\r | |
9 | #include <Base.h>\r | |
10 | #include <Library/ArmLib.h>\r | |
f977e650 | 11 | #include <Library/DebugLib.h>\r |
1e57a462 | 12 | #include <Library/PcdLib.h>\r |
13 | \r | |
cf580da1 | 14 | STATIC\r |
1e57a462 | 15 | VOID\r |
16 | CacheRangeOperation (\r | |
17 | IN VOID *Start,\r | |
18 | IN UINTN Length,\r | |
cf580da1 AB |
19 | IN LINE_OPERATION LineOperation,\r |
20 | IN UINTN LineLength\r | |
1e57a462 | 21 | )\r |
22 | {\r | |
cf580da1 | 23 | UINTN ArmCacheLineAlignmentMask = LineLength - 1;\r |
3402aac7 | 24 | \r |
6ea34e3a AB |
25 | // Align address (rounding down)\r |
26 | UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r | |
27 | UINTN EndAddress = (UINTN)Start + Length;\r | |
1e57a462 | 28 | \r |
6ea34e3a AB |
29 | // Perform the line operation on an address in each cache line\r |
30 | while (AlignedAddress < EndAddress) {\r | |
31 | LineOperation(AlignedAddress);\r | |
cf580da1 | 32 | AlignedAddress += LineLength;\r |
1e57a462 | 33 | }\r |
c7222893 | 34 | ArmDataSynchronizationBarrier ();\r |
1e57a462 | 35 | }\r |
36 | \r | |
37 | VOID\r | |
38 | EFIAPI\r | |
39 | InvalidateInstructionCache (\r | |
40 | VOID\r | |
41 | )\r | |
42 | {\r | |
ce6aec3e | 43 | ASSERT (FALSE);\r |
1e57a462 | 44 | }\r |
45 | \r | |
46 | VOID\r | |
47 | EFIAPI\r | |
48 | InvalidateDataCache (\r | |
49 | VOID\r | |
50 | )\r | |
51 | {\r | |
f977e650 | 52 | ASSERT (FALSE);\r |
1e57a462 | 53 | }\r |
54 | \r | |
55 | VOID *\r | |
56 | EFIAPI\r | |
57 | InvalidateInstructionCacheRange (\r | |
58 | IN VOID *Address,\r | |
59 | IN UINTN Length\r | |
60 | )\r | |
61 | {\r | |
cf580da1 AB |
62 | CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,\r |
63 | ArmDataCacheLineLength ());\r | |
64 | CacheRangeOperation (Address, Length,\r | |
65 | ArmInvalidateInstructionCacheEntryToPoUByMVA,\r | |
66 | ArmInstructionCacheLineLength ());\r | |
67 | \r | |
68 | ArmInstructionSynchronizationBarrier ();\r | |
69 | \r | |
1e57a462 | 70 | return Address;\r |
71 | }\r | |
72 | \r | |
73 | VOID\r | |
74 | EFIAPI\r | |
75 | WriteBackInvalidateDataCache (\r | |
76 | VOID\r | |
77 | )\r | |
78 | {\r | |
f977e650 | 79 | ASSERT (FALSE);\r |
1e57a462 | 80 | }\r |
81 | \r | |
82 | VOID *\r | |
83 | EFIAPI\r | |
84 | WriteBackInvalidateDataCacheRange (\r | |
85 | IN VOID *Address,\r | |
86 | IN UINTN Length\r | |
87 | )\r | |
88 | {\r | |
cf580da1 AB |
89 | CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,\r |
90 | ArmDataCacheLineLength ());\r | |
1e57a462 | 91 | return Address;\r |
92 | }\r | |
93 | \r | |
94 | VOID\r | |
95 | EFIAPI\r | |
96 | WriteBackDataCache (\r | |
97 | VOID\r | |
98 | )\r | |
99 | {\r | |
f977e650 | 100 | ASSERT (FALSE);\r |
1e57a462 | 101 | }\r |
102 | \r | |
103 | VOID *\r | |
104 | EFIAPI\r | |
105 | WriteBackDataCacheRange (\r | |
106 | IN VOID *Address,\r | |
107 | IN UINTN Length\r | |
108 | )\r | |
109 | {\r | |
cf580da1 AB |
110 | CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,\r |
111 | ArmDataCacheLineLength ());\r | |
1e57a462 | 112 | return Address;\r |
113 | }\r | |
114 | \r | |
115 | VOID *\r | |
116 | EFIAPI\r | |
117 | InvalidateDataCacheRange (\r | |
118 | IN VOID *Address,\r | |
119 | IN UINTN Length\r | |
120 | )\r | |
121 | {\r | |
cf580da1 AB |
122 | CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,\r |
123 | ArmDataCacheLineLength ());\r | |
1e57a462 | 124 | return Address;\r |
125 | }\r |