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5f525769 OM |
1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
4059386c | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
5f525769 OM |
6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #include <Library/ArmLib.h>\r | |
10 | #include <Library/ArmGicLib.h>\r | |
11 | \r | |
429309e0 | 12 | STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;\r |
f94522c8 AB |
13 | \r |
14 | RETURN_STATUS\r | |
5f525769 | 15 | EFIAPI\r |
f94522c8 | 16 | ArmGicArchLibInitialize (\r |
5f525769 OM |
17 | VOID\r |
18 | )\r | |
19 | {\r | |
429309e0 | 20 | UINT32 IccSre;\r |
eadbec01 | 21 | \r |
5f525769 OM |
22 | // Ideally we would like to use the GICC IIDR Architecture version here, but\r |
23 | // this does not seem to be very reliable as the implementation could easily\r | |
24 | // get it wrong. It is more reliable to check if the GICv3 System Register\r | |
25 | // feature is implemented on the CPU. This is also convenient as our GICv3\r | |
26 | // driver requires SRE. If only Memory mapped access is available we try to\r | |
27 | // drive the GIC as a v2.\r | |
b7ae5efb | 28 | if (ArmHasGicSystemRegisters ()) {\r |
37ec4d9a AB |
29 | // Make sure System Register access is enabled (SRE). This depends on the\r |
30 | // higher privilege level giving us permission, otherwise we will either\r | |
31 | // cause an exception here, or the write doesn't stick in which case we need\r | |
32 | // to fall back to the GICv2 MMIO interface.\r | |
33 | // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started\r | |
34 | // at the same exception level.\r | |
35 | // It is the OS responsibility to set this bit.\r | |
eadbec01 AB |
36 | IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r |
37 | if (!(IccSre & ICC_SRE_EL2_SRE)) {\r | |
38 | ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);\r | |
39 | IccSre = ArmGicV3GetControlSystemRegisterEnable ();\r | |
40 | }\r | |
429309e0 | 41 | \r |
eadbec01 | 42 | if (IccSre & ICC_SRE_EL2_SRE) {\r |
f94522c8 AB |
43 | mGicArchRevision = ARM_GIC_ARCH_REVISION_3;\r |
44 | goto Done;\r | |
37ec4d9a | 45 | }\r |
5f525769 OM |
46 | }\r |
47 | \r | |
f94522c8 AB |
48 | mGicArchRevision = ARM_GIC_ARCH_REVISION_2;\r |
49 | \r | |
50 | Done:\r | |
51 | return RETURN_SUCCESS;\r | |
52 | }\r | |
53 | \r | |
54 | ARM_GIC_ARCH_REVISION\r | |
55 | EFIAPI\r | |
56 | ArmGicGetSupportedArchRevision (\r | |
57 | VOID\r | |
58 | )\r | |
59 | {\r | |
60 | return mGicArchRevision;\r | |
5f525769 | 61 | }\r |