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25402f5d HL |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
01674afd | 4 | Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r |
6e131aff | 5 | Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r |
25402f5d | 6 | \r |
4059386c | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
25402f5d HL |
8 | \r |
9 | **/\r | |
10 | \r | |
b58ec859 AB |
11 | #include <Base.h>\r |
12 | \r | |
25402f5d | 13 | #include <Library/ArmLib.h>\r |
a2ab46ad | 14 | #include <Library/DebugLib.h>\r |
b58ec859 AB |
15 | \r |
16 | #include <Chipset/AArch64.h>\r | |
17 | \r | |
25402f5d HL |
18 | #include "AArch64Lib.h"\r |
19 | #include "ArmLibPrivate.h"\r | |
20 | \r | |
25402f5d HL |
21 | VOID\r |
22 | AArch64DataCacheOperation (\r | |
23 | IN AARCH64_CACHE_OPERATION DataCacheOperation\r | |
24 | )\r | |
25 | {\r | |
429309e0 | 26 | UINTN SavedInterruptState;\r |
25402f5d HL |
27 | \r |
28 | SavedInterruptState = ArmGetInterruptState ();\r | |
429309e0 | 29 | ArmDisableInterrupts ();\r |
25402f5d HL |
30 | \r |
31 | AArch64AllDataCachesOperation (DataCacheOperation);\r | |
32 | \r | |
3b149515 | 33 | ArmDataSynchronizationBarrier ();\r |
25402f5d HL |
34 | \r |
35 | if (SavedInterruptState) {\r | |
36 | ArmEnableInterrupts ();\r | |
37 | }\r | |
38 | }\r | |
39 | \r | |
25402f5d HL |
40 | VOID\r |
41 | EFIAPI\r | |
42 | ArmInvalidateDataCache (\r | |
43 | VOID\r | |
44 | )\r | |
45 | {\r | |
a2ab46ad AB |
46 | ASSERT (!ArmMmuEnabled ());\r |
47 | \r | |
3b149515 | 48 | ArmDataSynchronizationBarrier ();\r |
25402f5d HL |
49 | AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r |
50 | }\r | |
51 | \r | |
52 | VOID\r | |
53 | EFIAPI\r | |
54 | ArmCleanInvalidateDataCache (\r | |
55 | VOID\r | |
56 | )\r | |
57 | {\r | |
a2ab46ad AB |
58 | ASSERT (!ArmMmuEnabled ());\r |
59 | \r | |
3b149515 | 60 | ArmDataSynchronizationBarrier ();\r |
25402f5d HL |
61 | AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r |
62 | }\r | |
63 | \r | |
64 | VOID\r | |
65 | EFIAPI\r | |
66 | ArmCleanDataCache (\r | |
67 | VOID\r | |
68 | )\r | |
69 | {\r | |
a2ab46ad AB |
70 | ASSERT (!ArmMmuEnabled ());\r |
71 | \r | |
3b149515 | 72 | ArmDataSynchronizationBarrier ();\r |
25402f5d HL |
73 | AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r |
74 | }\r | |
5cc25cff LL |
75 | \r |
76 | /**\r | |
77 | Check whether the CPU supports the GIC system register interface (any version)\r | |
78 | \r | |
79 | @return Whether GIC System Register Interface is supported\r | |
80 | \r | |
81 | **/\r | |
82 | BOOLEAN\r | |
83 | EFIAPI\r | |
84 | ArmHasGicSystemRegisters (\r | |
85 | VOID\r | |
86 | )\r | |
87 | {\r | |
bb56ce81 | 88 | return ((ArmReadIdAA64Pfr0 () & AARCH64_PFR0_GIC) != 0);\r |
5cc25cff | 89 | }\r |
6e131aff RC |
90 | \r |
91 | /** Checks if CCIDX is implemented.\r | |
92 | \r | |
93 | @retval TRUE CCIDX is implemented.\r | |
94 | @retval FALSE CCIDX is not implemented.\r | |
95 | **/\r | |
96 | BOOLEAN\r | |
97 | EFIAPI\r | |
98 | ArmHasCcidx (\r | |
99 | VOID\r | |
100 | )\r | |
101 | {\r | |
429309e0 | 102 | UINTN Mmfr2;\r |
6e131aff RC |
103 | \r |
104 | Mmfr2 = ArmReadIdAA64Mmfr2 ();\r | |
105 | return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;\r | |
106 | }\r |