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25402f5d HL |
1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
3 | # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
9401d6f4 | 4 | # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
25402f5d HL |
6 | #\r |
7 | # This program and the accompanying materials\r | |
8 | # are licensed and made available under the terms and conditions of the BSD License\r | |
9 | # which accompanies this distribution. The full text of the license may be found at\r | |
10 | # http://opensource.org/licenses/bsd-license.php\r | |
11 | #\r | |
12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | #\r | |
15 | #------------------------------------------------------------------------------\r | |
16 | \r | |
17 | #include <Chipset/AArch64.h>\r | |
18 | #include <AsmMacroIoLibV8.h>\r | |
19 | \r | |
25402f5d HL |
20 | .set CTRL_M_BIT, (1 << 0)\r |
21 | .set CTRL_A_BIT, (1 << 1)\r | |
22 | .set CTRL_C_BIT, (1 << 2)\r | |
23 | .set CTRL_I_BIT, (1 << 12)\r | |
24 | .set CTRL_V_BIT, (1 << 12)\r | |
25 | .set CPACR_VFP_BITS, (3 << 20)\r | |
26 | \r | |
0efaa42f | 27 | ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r |
25402f5d | 28 | dc ivac, x0 // Invalidate single data cache line\r |
25402f5d HL |
29 | ret\r |
30 | \r | |
31 | \r | |
0efaa42f | 32 | ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r |
25402f5d | 33 | dc cvac, x0 // Clean single data cache line\r |
25402f5d HL |
34 | ret\r |
35 | \r | |
36 | \r | |
0efaa42f | 37 | ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r |
b7de7e3c EC |
38 | dc cvau, x0 // Clean single data cache line to PoU\r |
39 | ret\r | |
40 | \r | |
0efaa42f | 41 | ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r |
cf580da1 AB |
42 | ic ivau, x0 // Invalidate single instruction cache line to PoU\r |
43 | ret\r | |
44 | \r | |
b7de7e3c | 45 | \r |
0efaa42f | 46 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r |
25402f5d | 47 | dc civac, x0 // Clean and invalidate single data cache line\r |
25402f5d HL |
48 | ret\r |
49 | \r | |
50 | \r | |
0efaa42f | 51 | ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r |
25402f5d | 52 | dc isw, x0 // Invalidate this line\r |
25402f5d HL |
53 | ret\r |
54 | \r | |
55 | \r | |
0efaa42f | 56 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r |
25402f5d | 57 | dc cisw, x0 // Clean and Invalidate this line\r |
25402f5d HL |
58 | ret\r |
59 | \r | |
60 | \r | |
0efaa42f | 61 | ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r |
25402f5d | 62 | dc csw, x0 // Clean this line\r |
25402f5d HL |
63 | ret\r |
64 | \r | |
65 | \r | |
0efaa42f | 66 | ASM_FUNC(ArmInvalidateInstructionCache)\r |
25402f5d HL |
67 | ic iallu // Invalidate entire instruction cache\r |
68 | dsb sy\r | |
69 | isb\r | |
70 | ret\r | |
71 | \r | |
72 | \r | |
0efaa42f | 73 | ASM_FUNC(ArmEnableMmu)\r |
25402f5d HL |
74 | EL1_OR_EL2_OR_EL3(x1)\r |
75 | 1: mrs x0, sctlr_el1 // Read System control register EL1\r | |
76 | b 4f\r | |
77 | 2: mrs x0, sctlr_el2 // Read System control register EL2\r | |
78 | b 4f\r | |
79 | 3: mrs x0, sctlr_el3 // Read System control register EL3\r | |
80 | 4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit\r | |
81 | EL1_OR_EL2_OR_EL3(x1)\r | |
70f89c0b | 82 | 1: tlbi vmalle1\r |
ee95f9e1 | 83 | dsb nsh\r |
25402f5d HL |
84 | isb\r |
85 | msr sctlr_el1, x0 // Write back\r | |
86 | b 4f\r | |
87 | 2: tlbi alle2\r | |
ee95f9e1 | 88 | dsb nsh\r |
25402f5d HL |
89 | isb\r |
90 | msr sctlr_el2, x0 // Write back\r | |
91 | b 4f\r | |
92 | 3: tlbi alle3\r | |
ee95f9e1 | 93 | dsb nsh\r |
25402f5d HL |
94 | isb\r |
95 | msr sctlr_el3, x0 // Write back\r | |
ee95f9e1 | 96 | 4: isb\r |
25402f5d HL |
97 | ret\r |
98 | \r | |
99 | \r | |
0efaa42f | 100 | ASM_FUNC(ArmDisableMmu)\r |
25402f5d HL |
101 | EL1_OR_EL2_OR_EL3(x1)\r |
102 | 1: mrs x0, sctlr_el1 // Read System Control Register EL1\r | |
103 | b 4f\r | |
104 | 2: mrs x0, sctlr_el2 // Read System Control Register EL2\r | |
105 | b 4f\r | |
106 | 3: mrs x0, sctlr_el3 // Read System Control Register EL3\r | |
73ca5009 | 107 | 4: and x0, x0, #~CTRL_M_BIT // Clear MMU enable bit\r |
25402f5d HL |
108 | EL1_OR_EL2_OR_EL3(x1)\r |
109 | 1: msr sctlr_el1, x0 // Write back\r | |
70f89c0b | 110 | tlbi vmalle1\r |
25402f5d HL |
111 | b 4f\r |
112 | 2: msr sctlr_el2, x0 // Write back\r | |
113 | tlbi alle2\r | |
114 | b 4f\r | |
115 | 3: msr sctlr_el3, x0 // Write back\r | |
116 | tlbi alle3\r | |
117 | 4: dsb sy\r | |
118 | isb\r | |
119 | ret\r | |
120 | \r | |
121 | \r | |
0efaa42f | 122 | ASM_FUNC(ArmDisableCachesAndMmu)\r |
25402f5d HL |
123 | EL1_OR_EL2_OR_EL3(x1)\r |
124 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
125 | b 4f\r | |
126 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
127 | b 4f\r | |
128 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 BJ |
129 | 4: mov x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT) // Disable MMU, D & I caches\r |
130 | and x0, x0, x1\r | |
25402f5d HL |
131 | EL1_OR_EL2_OR_EL3(x1)\r |
132 | 1: msr sctlr_el1, x0 // Write back control register\r | |
133 | b 4f\r | |
134 | 2: msr sctlr_el2, x0 // Write back control register\r | |
135 | b 4f\r | |
136 | 3: msr sctlr_el3, x0 // Write back control register\r | |
137 | 4: dsb sy\r | |
138 | isb\r | |
139 | ret\r | |
140 | \r | |
141 | \r | |
0efaa42f | 142 | ASM_FUNC(ArmMmuEnabled)\r |
25402f5d HL |
143 | EL1_OR_EL2_OR_EL3(x1)\r |
144 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
145 | b 4f\r | |
146 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
147 | b 4f\r | |
148 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
149 | 4: and x0, x0, #CTRL_M_BIT\r | |
150 | ret\r | |
151 | \r | |
152 | \r | |
0efaa42f | 153 | ASM_FUNC(ArmEnableDataCache)\r |
25402f5d HL |
154 | EL1_OR_EL2_OR_EL3(x1)\r |
155 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
156 | b 4f\r | |
157 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
158 | b 4f\r | |
159 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
160 | 4: orr x0, x0, #CTRL_C_BIT // Set C bit\r | |
161 | EL1_OR_EL2_OR_EL3(x1)\r | |
162 | 1: msr sctlr_el1, x0 // Write back control register\r | |
163 | b 4f\r | |
164 | 2: msr sctlr_el2, x0 // Write back control register\r | |
165 | b 4f\r | |
166 | 3: msr sctlr_el3, x0 // Write back control register\r | |
167 | 4: dsb sy\r | |
168 | isb\r | |
169 | ret\r | |
170 | \r | |
171 | \r | |
0efaa42f | 172 | ASM_FUNC(ArmDisableDataCache)\r |
25402f5d HL |
173 | EL1_OR_EL2_OR_EL3(x1)\r |
174 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
175 | b 4f\r | |
176 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
177 | b 4f\r | |
178 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 179 | 4: and x0, x0, #~CTRL_C_BIT // Clear C bit\r |
25402f5d HL |
180 | EL1_OR_EL2_OR_EL3(x1)\r |
181 | 1: msr sctlr_el1, x0 // Write back control register\r | |
182 | b 4f\r | |
183 | 2: msr sctlr_el2, x0 // Write back control register\r | |
184 | b 4f\r | |
185 | 3: msr sctlr_el3, x0 // Write back control register\r | |
186 | 4: dsb sy\r | |
187 | isb\r | |
188 | ret\r | |
189 | \r | |
190 | \r | |
0efaa42f | 191 | ASM_FUNC(ArmEnableInstructionCache)\r |
25402f5d HL |
192 | EL1_OR_EL2_OR_EL3(x1)\r |
193 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
194 | b 4f\r | |
195 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
196 | b 4f\r | |
197 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
198 | 4: orr x0, x0, #CTRL_I_BIT // Set I bit\r | |
199 | EL1_OR_EL2_OR_EL3(x1)\r | |
200 | 1: msr sctlr_el1, x0 // Write back control register\r | |
201 | b 4f\r | |
202 | 2: msr sctlr_el2, x0 // Write back control register\r | |
203 | b 4f\r | |
204 | 3: msr sctlr_el3, x0 // Write back control register\r | |
205 | 4: dsb sy\r | |
206 | isb\r | |
207 | ret\r | |
208 | \r | |
209 | \r | |
0efaa42f | 210 | ASM_FUNC(ArmDisableInstructionCache)\r |
25402f5d HL |
211 | EL1_OR_EL2_OR_EL3(x1)\r |
212 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
213 | b 4f\r | |
214 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
215 | b 4f\r | |
216 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 217 | 4: and x0, x0, #~CTRL_I_BIT // Clear I bit\r |
25402f5d HL |
218 | EL1_OR_EL2_OR_EL3(x1)\r |
219 | 1: msr sctlr_el1, x0 // Write back control register\r | |
220 | b 4f\r | |
221 | 2: msr sctlr_el2, x0 // Write back control register\r | |
222 | b 4f\r | |
223 | 3: msr sctlr_el3, x0 // Write back control register\r | |
224 | 4: dsb sy\r | |
225 | isb\r | |
226 | ret\r | |
227 | \r | |
228 | \r | |
0efaa42f | 229 | ASM_FUNC(ArmEnableAlignmentCheck)\r |
25402f5d HL |
230 | EL1_OR_EL2(x1)\r |
231 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
232 | b 3f\r | |
233 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
234 | 3: orr x0, x0, #CTRL_A_BIT // Set A (alignment check) bit\r | |
235 | EL1_OR_EL2(x1)\r | |
236 | 1: msr sctlr_el1, x0 // Write back control register\r | |
237 | b 3f\r | |
238 | 2: msr sctlr_el2, x0 // Write back control register\r | |
239 | 3: dsb sy\r | |
240 | isb\r | |
241 | ret\r | |
242 | \r | |
243 | \r | |
0efaa42f | 244 | ASM_FUNC(ArmDisableAlignmentCheck)\r |
25402f5d HL |
245 | EL1_OR_EL2_OR_EL3(x1)\r |
246 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
247 | b 4f\r | |
248 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
249 | b 4f\r | |
250 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 251 | 4: and x0, x0, #~CTRL_A_BIT // Clear A (alignment check) bit\r |
25402f5d HL |
252 | EL1_OR_EL2_OR_EL3(x1)\r |
253 | 1: msr sctlr_el1, x0 // Write back control register\r | |
254 | b 4f\r | |
255 | 2: msr sctlr_el2, x0 // Write back control register\r | |
256 | b 4f\r | |
257 | 3: msr sctlr_el3, x0 // Write back control register\r | |
258 | 4: dsb sy\r | |
259 | isb\r | |
260 | ret\r | |
261 | \r | |
262 | \r | |
263 | // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now\r | |
0efaa42f | 264 | ASM_FUNC(ArmEnableBranchPrediction)\r |
25402f5d HL |
265 | ret\r |
266 | \r | |
267 | \r | |
268 | // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.\r | |
0efaa42f | 269 | ASM_FUNC(ArmDisableBranchPrediction)\r |
25402f5d HL |
270 | ret\r |
271 | \r | |
272 | \r | |
0efaa42f | 273 | ASM_FUNC(AArch64AllDataCachesOperation)\r |
25402f5d | 274 | // We can use regs 0-7 and 9-15 without having to save/restore.\r |
fb7ea611 | 275 | // Save our link register on the stack. - The stack must always be quad-word aligned\r |
de2a7824 AB |
276 | stp x29, x30, [sp, #-16]!\r |
277 | mov x29, sp\r | |
25402f5d HL |
278 | mov x1, x0 // Save Function call in x1\r |
279 | mrs x6, clidr_el1 // Read EL1 CLIDR\r | |
280 | and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)\r | |
433a49a0 OM |
281 | lsr x3, x3, #23 // Left align cache level value - the level is shifted by 1 to the\r |
282 | // right to ease the access to CSSELR and the Set/Way operation.\r | |
25402f5d HL |
283 | cbz x3, L_Finished // No need to clean if LoC is 0\r |
284 | mov x10, #0 // Start clean at cache level 0\r | |
25402f5d HL |
285 | \r |
286 | Loop1:\r | |
287 | add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info\r | |
288 | lsr x12, x6, x2 // bottom 3 bits are the Cache type for this level\r | |
289 | and x12, x12, #7 // get those 3 bits alone\r | |
290 | cmp x12, #2 // what cache at this level?\r | |
291 | b.lt L_Skip // no cache or only instruction cache at this level\r | |
292 | msr csselr_el1, x10 // write the Cache Size selection register with current level (CSSELR)\r | |
293 | isb // isb to sync the change to the CacheSizeID reg\r | |
294 | mrs x12, ccsidr_el1 // reads current Cache Size ID register (CCSIDR)\r | |
295 | and x2, x12, #0x7 // extract the line length field\r | |
296 | add x2, x2, #4 // add 4 for the line length offset (log2 16 bytes)\r | |
297 | mov x4, #0x400\r | |
298 | sub x4, x4, #1\r | |
299 | and x4, x4, x12, lsr #3 // x4 is the max number on the way size (right aligned)\r | |
300 | clz w5, w4 // w5 is the bit position of the way size increment\r | |
301 | mov x7, #0x00008000\r | |
302 | sub x7, x7, #1\r | |
303 | and x7, x7, x12, lsr #13 // x7 is the max number of the index size (right aligned)\r | |
304 | \r | |
305 | Loop2:\r | |
306 | mov x9, x4 // x9 working copy of the max way size (right aligned)\r | |
307 | \r | |
308 | Loop3:\r | |
309 | lsl x11, x9, x5\r | |
310 | orr x0, x10, x11 // factor in the way number and cache number\r | |
311 | lsl x11, x7, x2\r | |
312 | orr x0, x0, x11 // factor in the index number\r | |
313 | \r | |
314 | blr x1 // Goto requested cache operation\r | |
315 | \r | |
316 | subs x9, x9, #1 // decrement the way number\r | |
317 | b.ge Loop3\r | |
318 | subs x7, x7, #1 // decrement the index\r | |
319 | b.ge Loop2\r | |
320 | L_Skip:\r | |
321 | add x10, x10, #2 // increment the cache number\r | |
322 | cmp x3, x10\r | |
323 | b.gt Loop1\r | |
324 | \r | |
325 | L_Finished:\r | |
326 | dsb sy\r | |
327 | isb\r | |
de2a7824 | 328 | ldp x29, x30, [sp], #0x10\r |
25402f5d HL |
329 | ret\r |
330 | \r | |
331 | \r | |
0efaa42f | 332 | ASM_FUNC(ArmDataMemoryBarrier)\r |
25402f5d HL |
333 | dmb sy\r |
334 | ret\r | |
335 | \r | |
336 | \r | |
0efaa42f | 337 | ASM_FUNC(ArmDataSynchronizationBarrier)\r |
25402f5d HL |
338 | dsb sy\r |
339 | ret\r | |
340 | \r | |
341 | \r | |
0efaa42f | 342 | ASM_FUNC(ArmInstructionSynchronizationBarrier)\r |
25402f5d HL |
343 | isb\r |
344 | ret\r | |
345 | \r | |
346 | \r | |
0efaa42f | 347 | ASM_FUNC(ArmWriteVBar)\r |
25402f5d HL |
348 | EL1_OR_EL2_OR_EL3(x1)\r |
349 | 1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register\r | |
350 | b 4f\r | |
351 | 2: msr vbar_el2, x0 // Set the Address of the EL2 Vector Table in the VBAR register\r | |
352 | b 4f\r | |
353 | 3: msr vbar_el3, x0 // Set the Address of the EL3 Vector Table in the VBAR register\r | |
354 | 4: isb\r | |
355 | ret\r | |
356 | \r | |
0efaa42f | 357 | ASM_FUNC(ArmReadVBar)\r |
f0247796 OM |
358 | EL1_OR_EL2_OR_EL3(x1)\r |
359 | 1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register\r | |
360 | ret\r | |
361 | 2: mrs x0, vbar_el2 // Set the Address of the EL2 Vector Table in the VBAR register\r | |
362 | ret\r | |
363 | 3: mrs x0, vbar_el3 // Set the Address of the EL3 Vector Table in the VBAR register\r | |
364 | ret\r | |
365 | \r | |
366 | \r | |
0efaa42f | 367 | ASM_FUNC(ArmEnableVFP)\r |
25402f5d HL |
368 | // Check whether floating-point is implemented in the processor.\r |
369 | mov x1, x30 // Save LR\r | |
370 | bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)\r | |
371 | mov x30, x1 // Restore LR\r | |
372 | ands x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation\r | |
373 | cmp x0, #0 // VFP is implemented if '0'.\r | |
374 | b.ne 4f // Exit if VFP not implemented.\r | |
375 | // FVP is implemented.\r | |
376 | // Make sure VFP exceptions are not trapped (to any exception level).\r | |
377 | mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR)\r | |
378 | orr x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1\r | |
379 | msr cpacr_el1, x0 // Write back EL1 Coprocessor Access Control Register (CPACR)\r | |
380 | mov x1, #AARCH64_CPTR_TFP // TFP Bit for trapping VFP Exceptions\r | |
381 | EL1_OR_EL2_OR_EL3(x2)\r | |
382 | 1:ret // Not configurable in EL1\r | |
383 | 2:mrs x0, cptr_el2 // Disable VFP traps to EL2\r | |
384 | bic x0, x0, x1\r | |
385 | msr cptr_el2, x0\r | |
386 | ret\r | |
387 | 3:mrs x0, cptr_el3 // Disable VFP traps to EL3\r | |
388 | bic x0, x0, x1\r | |
389 | msr cptr_el3, x0\r | |
390 | 4:ret\r | |
391 | \r | |
392 | \r | |
0efaa42f | 393 | ASM_FUNC(ArmCallWFI)\r |
25402f5d HL |
394 | wfi\r |
395 | ret\r | |
396 | \r | |
397 | \r | |
0efaa42f | 398 | ASM_FUNC(ArmReadMpidr)\r |
25402f5d HL |
399 | mrs x0, mpidr_el1 // read EL1 MPIDR\r |
400 | ret\r | |
401 | \r | |
402 | \r | |
403 | // Keep old function names for C compatibilty for now. Change later?\r | |
0efaa42f | 404 | ASM_FUNC(ArmReadTpidrurw)\r |
25402f5d HL |
405 | mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r |
406 | ret\r | |
407 | \r | |
408 | \r | |
409 | // Keep old function names for C compatibilty for now. Change later?\r | |
0efaa42f | 410 | ASM_FUNC(ArmWriteTpidrurw)\r |
25402f5d HL |
411 | msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r |
412 | ret\r | |
413 | \r | |
414 | \r | |
415 | // Arch timers are mandatory on AArch64\r | |
0efaa42f | 416 | ASM_FUNC(ArmIsArchTimerImplemented)\r |
25402f5d HL |
417 | mov x0, #1\r |
418 | ret\r | |
419 | \r | |
420 | \r | |
0efaa42f | 421 | ASM_FUNC(ArmReadIdPfr0)\r |
25402f5d HL |
422 | mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register\r |
423 | ret\r | |
424 | \r | |
425 | \r | |
426 | // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?\r | |
427 | // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.\r | |
428 | // See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c\r | |
429 | // Not defined yet, but stick in here for now, should read all zeros.\r | |
0efaa42f | 430 | ASM_FUNC(ArmReadIdPfr1)\r |
25402f5d HL |
431 | mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register\r |
432 | ret\r | |
433 | \r | |
434 | // VOID ArmWriteHcr(UINTN Hcr)\r | |
0efaa42f | 435 | ASM_FUNC(ArmWriteHcr)\r |
25402f5d HL |
436 | msr hcr_el2, x0 // Write the passed HCR value\r |
437 | ret\r | |
438 | \r | |
d2bb61a2 | 439 | // UINTN ArmReadHcr(VOID)\r |
0efaa42f | 440 | ASM_FUNC(ArmReadHcr)\r |
d2bb61a2 EC |
441 | mrs x0, hcr_el2\r |
442 | ret\r | |
443 | \r | |
25402f5d | 444 | // UINTN ArmReadCurrentEL(VOID)\r |
0efaa42f | 445 | ASM_FUNC(ArmReadCurrentEL)\r |
25402f5d HL |
446 | mrs x0, CurrentEL\r |
447 | ret\r | |
448 | \r | |
25402f5d | 449 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |