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Commit | Line | Data |
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25402f5d HL |
1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
51ad04cb | 4 | # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
25402f5d | 6 | #\r |
4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
25402f5d HL |
8 | #\r |
9 | #------------------------------------------------------------------------------\r | |
10 | \r | |
51ad04cb | 11 | #include <AsmMacroIoLibV8.h>\r |
25402f5d | 12 | \r |
25402f5d HL |
13 | .set MPIDR_U_BIT, (30)\r |
14 | .set MPIDR_U_MASK, (1 << MPIDR_U_BIT)\r | |
4af3dd80 EC |
15 | \r |
16 | // DAIF bit definitions for writing through msr daifclr/sr daifset\r | |
17 | .set DAIF_WR_FIQ_BIT, (1 << 0)\r | |
18 | .set DAIF_WR_IRQ_BIT, (1 << 1)\r | |
19 | .set DAIF_WR_ABORT_BIT, (1 << 2)\r | |
20 | .set DAIF_WR_DEBUG_BIT, (1 << 3)\r | |
21 | .set DAIF_WR_INT_BITS, (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)\r | |
22 | .set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)\r | |
25402f5d HL |
23 | \r |
24 | \r | |
0efaa42f | 25 | ASM_FUNC(ArmIsMpCore)\r |
ff5fef14 | 26 | mrs x0, mpidr_el1 // Read EL1 Multiprocessor Affinty Reg (MPIDR)\r |
25402f5d HL |
27 | and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system\r |
28 | lsr x0, x0, #MPIDR_U_BIT\r | |
29 | eor x0, x0, #1\r | |
30 | ret\r | |
31 | \r | |
32 | \r | |
0efaa42f | 33 | ASM_FUNC(ArmEnableAsynchronousAbort)\r |
4af3dd80 | 34 | msr daifclr, #DAIF_WR_ABORT_BIT\r |
25402f5d HL |
35 | isb\r |
36 | ret\r | |
37 | \r | |
38 | \r | |
0efaa42f | 39 | ASM_FUNC(ArmDisableAsynchronousAbort)\r |
4af3dd80 | 40 | msr daifset, #DAIF_WR_ABORT_BIT\r |
25402f5d HL |
41 | isb\r |
42 | ret\r | |
43 | \r | |
44 | \r | |
0efaa42f | 45 | ASM_FUNC(ArmEnableIrq)\r |
4af3dd80 | 46 | msr daifclr, #DAIF_WR_IRQ_BIT\r |
25402f5d HL |
47 | isb\r |
48 | ret\r | |
49 | \r | |
50 | \r | |
0efaa42f | 51 | ASM_FUNC(ArmDisableIrq)\r |
4af3dd80 | 52 | msr daifset, #DAIF_WR_IRQ_BIT\r |
25402f5d HL |
53 | isb\r |
54 | ret\r | |
55 | \r | |
56 | \r | |
0efaa42f | 57 | ASM_FUNC(ArmEnableFiq)\r |
4af3dd80 | 58 | msr daifclr, #DAIF_WR_FIQ_BIT\r |
25402f5d HL |
59 | isb\r |
60 | ret\r | |
61 | \r | |
62 | \r | |
0efaa42f | 63 | ASM_FUNC(ArmDisableFiq)\r |
4af3dd80 | 64 | msr daifset, #DAIF_WR_FIQ_BIT\r |
25402f5d HL |
65 | isb\r |
66 | ret\r | |
67 | \r | |
68 | \r | |
0efaa42f | 69 | ASM_FUNC(ArmEnableInterrupts)\r |
4af3dd80 | 70 | msr daifclr, #DAIF_WR_INT_BITS\r |
25402f5d HL |
71 | isb\r |
72 | ret\r | |
73 | \r | |
74 | \r | |
0efaa42f | 75 | ASM_FUNC(ArmDisableInterrupts)\r |
4af3dd80 | 76 | msr daifset, #DAIF_WR_INT_BITS\r |
25402f5d HL |
77 | isb\r |
78 | ret\r | |
79 | \r | |
80 | \r | |
0efaa42f | 81 | ASM_FUNC(ArmDisableAllExceptions)\r |
4af3dd80 | 82 | msr daifset, #DAIF_WR_ALL\r |
25402f5d HL |
83 | isb\r |
84 | ret\r | |
85 | \r | |
86 | \r | |
87 | // UINT32\r | |
88 | // ReadCCSIDR (\r | |
89 | // IN UINT32 CSSELR\r | |
90 | // )\r | |
0efaa42f | 91 | ASM_FUNC(ReadCCSIDR)\r |
25402f5d HL |
92 | msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR)\r |
93 | isb\r | |
94 | mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR)\r | |
95 | ret\r | |
96 | \r | |
97 | \r | |
98 | // UINT32\r | |
99 | // ReadCLIDR (\r | |
100 | // IN UINT32 CSSELR\r | |
101 | // )\r | |
0efaa42f | 102 | ASM_FUNC(ReadCLIDR)\r |
25402f5d HL |
103 | mrs x0, clidr_el1 // Read Cache Level ID Register\r |
104 | ret\r | |
105 | \r | |
106 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |