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Commit | Line | Data |
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3402aac7 | 1 | #------------------------------------------------------------------------------\r |
bd6b9799 | 2 | #\r |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
ff1f27c0 | 4 | # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r |
0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
bd6b9799 | 6 | #\r |
4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bd6b9799 | 8 | #\r |
9 | #------------------------------------------------------------------------------\r | |
10 | \r | |
11 | #include <AsmMacroIoLib.h>\r | |
12 | \r | |
0efaa42f | 13 | ASM_FUNC(ArmReadMidr)\r |
bd6b9799 | 14 | mrc p15,0,R0,c0,c0,0\r |
15 | bx LR\r | |
16 | \r | |
0efaa42f | 17 | ASM_FUNC(ArmCacheInfo)\r |
bd6b9799 | 18 | mrc p15,0,R0,c0,c0,1\r |
19 | bx LR\r | |
20 | \r | |
0efaa42f | 21 | ASM_FUNC(ArmGetInterruptState)\r |
bd6b9799 | 22 | mrs R0,CPSR\r |
23 | tst R0,#0x80 @Check if IRQ is enabled.\r | |
24 | moveq R0,#1\r | |
25 | movne R0,#0\r | |
26 | bx LR\r | |
27 | \r | |
0efaa42f | 28 | ASM_FUNC(ArmGetFiqState)\r |
bd6b9799 | 29 | mrs R0,CPSR\r |
30 | tst R0,#0x40 @Check if FIQ is enabled.\r | |
31 | moveq R0,#1\r | |
32 | movne R0,#0\r | |
33 | bx LR\r | |
34 | \r | |
0efaa42f | 35 | ASM_FUNC(ArmSetDomainAccessControl)\r |
bd6b9799 | 36 | mcr p15,0,r0,c3,c0,0\r |
37 | bx lr\r | |
38 | \r | |
0efaa42f | 39 | ASM_FUNC(CPSRMaskInsert) @ on entry, r0 is the mask and r1 is the field to insert\r |
bd6b9799 | 40 | stmfd sp!, {r4-r12, lr} @ save all the banked registers\r |
41 | mov r3, sp @ copy the stack pointer into a non-banked register\r | |
42 | mrs r2, cpsr @ read the cpsr\r | |
43 | bic r2, r2, r0 @ clear mask in the cpsr\r | |
44 | and r1, r1, r0 @ clear bits outside the mask in the input\r | |
45 | orr r2, r2, r1 @ set field\r | |
46 | msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r | |
47 | isb\r | |
48 | mov sp, r3 @ restore stack pointer\r | |
49 | ldmfd sp!, {r4-r12, lr} @ restore registers\r | |
27995cd5 | 50 | bx lr @ return (hopefully thumb-safe!)\r |
bd6b9799 | 51 | \r |
0efaa42f | 52 | ASM_FUNC(CPSRRead)\r |
bd6b9799 | 53 | mrs r0, cpsr\r |
54 | bx lr\r | |
55 | \r | |
0efaa42f | 56 | ASM_FUNC(ArmReadCpacr)\r |
836c3500 | 57 | mrc p15, 0, r0, c1, c0, 2\r |
58 | bx lr\r | |
59 | \r | |
0efaa42f | 60 | ASM_FUNC(ArmWriteCpacr)\r |
bd6b9799 | 61 | mcr p15, 0, r0, c1, c0, 2\r |
18029bb9 | 62 | isb\r |
bd6b9799 | 63 | bx lr\r |
64 | \r | |
0efaa42f | 65 | ASM_FUNC(ArmWriteAuxCr)\r |
bd6b9799 | 66 | mcr p15, 0, r0, c1, c0, 1\r |
67 | bx lr\r | |
68 | \r | |
0efaa42f | 69 | ASM_FUNC(ArmReadAuxCr)\r |
bd6b9799 | 70 | mrc p15, 0, r0, c1, c0, 1\r |
3402aac7 | 71 | bx lr\r |
bd6b9799 | 72 | \r |
0efaa42f | 73 | ASM_FUNC(ArmSetTTBR0)\r |
bd6b9799 | 74 | mcr p15,0,r0,c2,c0,0\r |
75 | isb\r | |
76 | bx lr\r | |
77 | \r | |
0efaa42f | 78 | ASM_FUNC(ArmSetTTBCR)\r |
ff1f27c0 EL |
79 | mcr p15, 0, r0, c2, c0, 2\r |
80 | isb\r | |
81 | bx lr\r | |
82 | \r | |
0efaa42f | 83 | ASM_FUNC(ArmGetTTBR0BaseAddress)\r |
bd6b9799 | 84 | mrc p15,0,r0,c2,c0,0\r |
0efaa42f | 85 | MOV32 (r1, 0xFFFFC000)\r |
bd6b9799 | 86 | and r0, r0, r1\r |
87 | isb\r | |
88 | bx lr\r | |
89 | \r | |
90 | //\r | |
91 | //VOID\r | |
92 | //ArmUpdateTranslationTableEntry (\r | |
93 | // IN VOID *TranslationTableEntry // R0\r | |
94 | // IN VOID *MVA // R1\r | |
95 | // );\r | |
0efaa42f | 96 | ASM_FUNC(ArmUpdateTranslationTableEntry)\r |
3402aac7 | 97 | mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA\r |
bd6b9799 | 98 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r |
99 | dsb\r | |
100 | isb\r | |
101 | bx lr\r | |
102 | \r | |
0efaa42f | 103 | ASM_FUNC(ArmInvalidateTlb)\r |
bd6b9799 | 104 | mov r0,#0\r |
105 | mcr p15,0,r0,c8,c7,0\r | |
106 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
107 | dsb\r | |
108 | isb\r | |
109 | bx lr\r | |
110 | \r | |
0efaa42f | 111 | ASM_FUNC(ArmReadScr)\r |
836c3500 | 112 | mrc p15, 0, r0, c1, c1, 0\r |
113 | bx lr\r | |
114 | \r | |
0efaa42f | 115 | ASM_FUNC(ArmWriteScr)\r |
bd6b9799 | 116 | mcr p15, 0, r0, c1, c1, 0\r |
b2d0e0c5 | 117 | isb\r |
bd6b9799 | 118 | bx lr\r |
119 | \r | |
0efaa42f | 120 | ASM_FUNC(ArmReadHVBar)\r |
5ea2c2d3 | 121 | mrc p15, 4, r0, c12, c0, 0\r |
122 | bx lr\r | |
123 | \r | |
0efaa42f | 124 | ASM_FUNC(ArmWriteHVBar)\r |
5ea2c2d3 | 125 | mcr p15, 4, r0, c12, c0, 0\r |
126 | bx lr\r | |
127 | \r | |
0efaa42f | 128 | ASM_FUNC(ArmReadMVBar)\r |
836c3500 | 129 | mrc p15, 0, r0, c12, c0, 1\r |
130 | bx lr\r | |
131 | \r | |
0efaa42f | 132 | ASM_FUNC(ArmWriteMVBar)\r |
bd6b9799 | 133 | mcr p15, 0, r0, c12, c0, 1\r |
134 | bx lr\r | |
135 | \r | |
0efaa42f | 136 | ASM_FUNC(ArmCallWFE)\r |
b1d41be7 | 137 | wfe\r |
138 | bx lr\r | |
139 | \r | |
0efaa42f | 140 | ASM_FUNC(ArmCallSEV)\r |
b1d41be7 | 141 | sev\r |
142 | bx lr\r | |
143 | \r | |
0efaa42f | 144 | ASM_FUNC(ArmReadSctlr)\r |
52d44f77 OM |
145 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r |
146 | bx lr\r | |
147 | \r | |
1e1d1697 MZ |
148 | ASM_FUNC(ArmWriteSctlr)\r |
149 | mcr p15, 0, r0, c1, c0, 0\r | |
150 | bx lr\r | |
151 | \r | |
0efaa42f | 152 | ASM_FUNC(ArmReadCpuActlr)\r |
52d44f77 OM |
153 | mrc p15, 0, r0, c1, c0, 1\r |
154 | bx lr\r | |
155 | \r | |
0efaa42f | 156 | ASM_FUNC(ArmWriteCpuActlr)\r |
52d44f77 OM |
157 | mcr p15, 0, r0, c1, c0, 1\r |
158 | dsb\r | |
159 | isb\r | |
160 | bx lr\r | |
836c3500 | 161 | \r |
95d04ebc AB |
162 | ASM_FUNC (ArmGetPhysicalAddressBits)\r |
163 | mrc p15, 0, r0, c0, c1, 4 // MMFR0\r | |
164 | and r0, r0, #0xf // VMSA [3:0]\r | |
165 | cmp r0, #5 // >= 5 implies LPAE support\r | |
166 | movlt r0, #32 // 32 bits if no LPAE\r | |
167 | movge r0, #40 // 40 bits if LPAE\r | |
168 | bx lr\r | |
169 | \r | |
bd6b9799 | 170 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |