ArmPkg/ArmLib: add support for reading the max physical address space size

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm / ArmLibSupport.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r
# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <AsmMacroIoLib.h>\r
\r
ASM_FUNC(ArmReadMidr)\r
  mrc     p15,0,R0,c0,c0,0\r
  bx      LR\r
\r
ASM_FUNC(ArmCacheInfo)\r
  mrc     p15,0,R0,c0,c0,1\r
  bx      LR\r
\r
ASM_FUNC(ArmGetInterruptState)\r
  mrs     R0,CPSR\r
  tst     R0,#0x80      @Check if IRQ is enabled.\r
  moveq   R0,#1\r
  movne   R0,#0\r
  bx      LR\r
\r
ASM_FUNC(ArmGetFiqState)\r
  mrs     R0,CPSR\r
  tst     R0,#0x40      @Check if FIQ is enabled.\r
  moveq   R0,#1\r
  movne   R0,#0\r
  bx      LR\r
\r
ASM_FUNC(ArmSetDomainAccessControl)\r
  mcr     p15,0,r0,c3,c0,0\r
  bx      lr\r
\r
ASM_FUNC(CPSRMaskInsert)    @ on entry, r0 is the mask and r1 is the field to insert\r
  stmfd   sp!, {r4-r12, lr} @ save all the banked registers\r
  mov     r3, sp            @ copy the stack pointer into a non-banked register\r
  mrs     r2, cpsr          @ read the cpsr\r
  bic     r2, r2, r0        @ clear mask in the cpsr\r
  and     r1, r1, r0        @ clear bits outside the mask in the input\r
  orr     r2, r2, r1        @ set field\r
  msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)\r
  isb\r
  mov     sp, r3            @ restore stack pointer\r
  ldmfd   sp!, {r4-r12, lr} @ restore registers\r
  bx      lr                @ return (hopefully thumb-safe!)\r
\r
ASM_FUNC(CPSRRead)\r
  mrs     r0, cpsr\r
  bx      lr\r
\r
ASM_FUNC(ArmReadCpacr)\r
  mrc     p15, 0, r0, c1, c0, 2\r
  bx      lr\r
\r
ASM_FUNC(ArmWriteCpacr)\r
  mcr     p15, 0, r0, c1, c0, 2\r
  isb\r
  bx      lr\r
\r
ASM_FUNC(ArmWriteAuxCr)\r
  mcr     p15, 0, r0, c1, c0, 1\r
  bx      lr\r
\r
ASM_FUNC(ArmReadAuxCr)\r
  mrc     p15, 0, r0, c1, c0, 1\r
  bx      lr\r
\r
ASM_FUNC(ArmSetTTBR0)\r
  mcr     p15,0,r0,c2,c0,0\r
  isb\r
  bx      lr\r
\r
ASM_FUNC(ArmSetTTBCR)\r
  mcr     p15, 0, r0, c2, c0, 2\r
  isb\r
  bx      lr\r
\r
ASM_FUNC(ArmGetTTBR0BaseAddress)\r
  mrc     p15,0,r0,c2,c0,0\r
  MOV32   (r1, 0xFFFFC000)\r
  and     r0, r0, r1\r
  isb\r
  bx      lr\r
\r
//\r
//VOID\r
//ArmUpdateTranslationTableEntry (\r
//  IN VOID  *TranslationTableEntry  // R0\r
//  IN VOID  *MVA                    // R1\r
//  );\r
ASM_FUNC(ArmUpdateTranslationTableEntry)\r
  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA\r
  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
  dsb\r
  isb\r
  bx      lr\r
\r
ASM_FUNC(ArmInvalidateTlb)\r
  mov     r0,#0\r
  mcr     p15,0,r0,c8,c7,0\r
  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r
  dsb\r
  isb\r
  bx      lr\r
\r
ASM_FUNC(ArmReadScr)\r
  mrc     p15, 0, r0, c1, c1, 0\r
  bx      lr\r
\r
ASM_FUNC(ArmWriteScr)\r
  mcr     p15, 0, r0, c1, c1, 0\r
  isb\r
  bx      lr\r
\r
ASM_FUNC(ArmReadHVBar)\r
  mrc     p15, 4, r0, c12, c0, 0\r
  bx      lr\r
\r
ASM_FUNC(ArmWriteHVBar)\r
  mcr     p15, 4, r0, c12, c0, 0\r
  bx      lr\r
\r
ASM_FUNC(ArmReadMVBar)\r
  mrc     p15, 0, r0, c12, c0, 1\r
  bx      lr\r
\r
ASM_FUNC(ArmWriteMVBar)\r
  mcr     p15, 0, r0, c12, c0, 1\r
  bx      lr\r
\r
ASM_FUNC(ArmCallWFE)\r
  wfe\r
  bx      lr\r
\r
ASM_FUNC(ArmCallSEV)\r
  sev\r
  bx      lr\r
\r
ASM_FUNC(ArmReadSctlr)\r
  mrc     p15, 0, r0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)\r
  bx      lr\r
\r
ASM_FUNC(ArmWriteSctlr)\r
  mcr     p15, 0, r0, c1, c0, 0\r
  bx      lr\r
\r
ASM_FUNC(ArmReadCpuActlr)\r
  mrc     p15, 0, r0, c1, c0, 1\r
  bx      lr\r
\r
ASM_FUNC(ArmWriteCpuActlr)\r
  mcr     p15, 0, r0, c1, c0, 1\r
  dsb\r
  isb\r
  bx      lr\r
\r
ASM_FUNC (ArmGetPhysicalAddressBits)\r
  mrc     p15, 0, r0, c0, c1, 4   // MMFR0\r
  and     r0, r0, #0xf            // VMSA [3:0]\r
  cmp     r0, #5                  // >= 5 implies LPAE support\r
  movlt   r0, #32                 // 32 bits if no LPAE\r
  movge   r0, #40                 // 40 bits if LPAE\r
  bx      lr\r
\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r