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3402aac7 | 1 | //------------------------------------------------------------------------------\r |
bd6b9799 | 2 | //\r |
3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
ff1f27c0 | 4 | // Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | //\r |
6 | // This program and the accompanying materials\r | |
7 | // are licensed and made available under the terms and conditions of the BSD License\r | |
8 | // which accompanies this distribution. The full text of the license may be found at\r | |
9 | // http://opensource.org/licenses/bsd-license.php\r | |
10 | //\r | |
11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | //\r | |
14 | //------------------------------------------------------------------------------\r | |
15 | \r | |
bd6b9799 | 16 | INCLUDE AsmMacroIoLib.inc\r |
17 | \r | |
efda1775 EC |
18 | \r |
19 | INCLUDE AsmMacroExport.inc\r | |
20 | \r | |
21 | RVCT_ASM_EXPORT ArmReadMidr\r | |
bd6b9799 | 22 | mrc p15,0,R0,c0,c0,0\r |
23 | bx LR\r | |
24 | \r | |
efda1775 | 25 | RVCT_ASM_EXPORT ArmCacheInfo\r |
bd6b9799 | 26 | mrc p15,0,R0,c0,c0,1\r |
27 | bx LR\r | |
28 | \r | |
efda1775 | 29 | RVCT_ASM_EXPORT ArmGetInterruptState\r |
bd6b9799 | 30 | mrs R0,CPSR\r |
31 | tst R0,#0x80 // Check if IRQ is enabled.\r | |
32 | moveq R0,#1\r | |
33 | movne R0,#0\r | |
34 | bx LR\r | |
35 | \r | |
efda1775 | 36 | RVCT_ASM_EXPORT ArmGetFiqState\r |
bd6b9799 | 37 | mrs R0,CPSR\r |
38 | tst R0,#0x40 // Check if FIQ is enabled.\r | |
39 | moveq R0,#1\r | |
40 | movne R0,#0\r | |
41 | bx LR\r | |
42 | \r | |
efda1775 | 43 | RVCT_ASM_EXPORT ArmSetDomainAccessControl\r |
bd6b9799 | 44 | mcr p15,0,r0,c3,c0,0\r |
45 | bx lr\r | |
46 | \r | |
efda1775 | 47 | RVCT_ASM_EXPORT CPSRMaskInsert\r |
bd6b9799 | 48 | stmfd sp!, {r4-r12, lr} // save all the banked registers\r |
49 | mov r3, sp // copy the stack pointer into a non-banked register\r | |
50 | mrs r2, cpsr // read the cpsr\r | |
51 | bic r2, r2, r0 // clear mask in the cpsr\r | |
52 | and r1, r1, r0 // clear bits outside the mask in the input\r | |
53 | orr r2, r2, r1 // set field\r | |
54 | msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r | |
55 | isb\r | |
56 | mov sp, r3 // restore stack pointer\r | |
57 | ldmfd sp!, {r4-r12, lr} // restore registers\r | |
58 | bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r | |
59 | \r | |
efda1775 | 60 | RVCT_ASM_EXPORT CPSRRead\r |
bd6b9799 | 61 | mrs r0, cpsr\r |
62 | bx lr\r | |
63 | \r | |
efda1775 | 64 | RVCT_ASM_EXPORT ArmReadCpacr\r |
836c3500 | 65 | mrc p15, 0, r0, c1, c0, 2\r |
66 | bx lr\r | |
67 | \r | |
efda1775 | 68 | RVCT_ASM_EXPORT ArmWriteCpacr\r |
bd6b9799 | 69 | mcr p15, 0, r0, c1, c0, 2\r |
18029bb9 | 70 | isb\r |
bd6b9799 | 71 | bx lr\r |
72 | \r | |
efda1775 | 73 | RVCT_ASM_EXPORT ArmWriteAuxCr\r |
bd6b9799 | 74 | mcr p15, 0, r0, c1, c0, 1\r |
75 | bx lr\r | |
76 | \r | |
efda1775 | 77 | RVCT_ASM_EXPORT ArmReadAuxCr\r |
bd6b9799 | 78 | mrc p15, 0, r0, c1, c0, 1\r |
3402aac7 | 79 | bx lr\r |
bd6b9799 | 80 | \r |
efda1775 | 81 | RVCT_ASM_EXPORT ArmSetTTBR0\r |
bd6b9799 | 82 | mcr p15,0,r0,c2,c0,0\r |
83 | isb\r | |
84 | bx lr\r | |
85 | \r | |
ff1f27c0 EL |
86 | RVCT_ASM_EXPORT ArmSetTTBCR\r |
87 | mcr p15, 0, r0, c2, c0, 2\r | |
88 | isb\r | |
89 | bx lr\r | |
90 | \r | |
efda1775 | 91 | RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r |
bd6b9799 | 92 | mrc p15,0,r0,c2,c0,0\r |
0efaa42f | 93 | MOV32 r1, 0xFFFFC000\r |
bd6b9799 | 94 | and r0, r0, r1\r |
95 | isb\r | |
96 | bx lr\r | |
97 | \r | |
98 | //\r | |
99 | //VOID\r | |
100 | //ArmUpdateTranslationTableEntry (\r | |
101 | // IN VOID *TranslationTableEntry // R0\r | |
102 | // IN VOID *MVA // R1\r | |
103 | // );\r | |
efda1775 | 104 | RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r |
bd6b9799 | 105 | mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r |
106 | dsb\r | |
107 | mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r | |
108 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
109 | dsb\r | |
110 | isb\r | |
111 | bx lr\r | |
112 | \r | |
efda1775 | 113 | RVCT_ASM_EXPORT ArmInvalidateTlb\r |
bd6b9799 | 114 | mov r0,#0\r |
115 | mcr p15,0,r0,c8,c7,0\r | |
116 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
117 | dsb\r | |
118 | isb\r | |
119 | bx lr\r | |
120 | \r | |
efda1775 | 121 | RVCT_ASM_EXPORT ArmReadScr\r |
836c3500 | 122 | mrc p15, 0, r0, c1, c1, 0\r |
123 | bx lr\r | |
124 | \r | |
efda1775 | 125 | RVCT_ASM_EXPORT ArmWriteScr\r |
bd6b9799 | 126 | mcr p15, 0, r0, c1, c1, 0\r |
b2d0e0c5 | 127 | isb\r |
bd6b9799 | 128 | bx lr\r |
129 | \r | |
efda1775 | 130 | RVCT_ASM_EXPORT ArmReadHVBar\r |
5ea2c2d3 | 131 | mrc p15, 4, r0, c12, c0, 0\r |
132 | bx lr\r | |
133 | \r | |
efda1775 | 134 | RVCT_ASM_EXPORT ArmWriteHVBar\r |
5ea2c2d3 | 135 | mcr p15, 4, r0, c12, c0, 0\r |
136 | bx lr\r | |
137 | \r | |
efda1775 | 138 | RVCT_ASM_EXPORT ArmReadMVBar\r |
836c3500 | 139 | mrc p15, 0, r0, c12, c0, 1\r |
140 | bx lr\r | |
141 | \r | |
efda1775 | 142 | RVCT_ASM_EXPORT ArmWriteMVBar\r |
bd6b9799 | 143 | mcr p15, 0, r0, c12, c0, 1\r |
144 | bx lr\r | |
3402aac7 | 145 | \r |
efda1775 | 146 | RVCT_ASM_EXPORT ArmCallWFE\r |
b1d41be7 | 147 | wfe\r |
27995cd5 | 148 | bx lr\r |
b1d41be7 | 149 | \r |
efda1775 | 150 | RVCT_ASM_EXPORT ArmCallSEV\r |
b1d41be7 | 151 | sev\r |
27995cd5 | 152 | bx lr\r |
b1d41be7 | 153 | \r |
efda1775 | 154 | RVCT_ASM_EXPORT ArmReadSctlr\r |
27995cd5 | 155 | mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r |
91c38d4e | 156 | bx lr\r |
52d44f77 | 157 | \r |
1e1d1697 MZ |
158 | RVCT_ASM_EXPORT ArmWriteSctlr\r |
159 | mcr p15, 0, r0, c1, c0, 0\r | |
160 | bx lr\r | |
52d44f77 | 161 | \r |
efda1775 | 162 | RVCT_ASM_EXPORT ArmReadCpuActlr\r |
52d44f77 OM |
163 | mrc p15, 0, r0, c1, c0, 1\r |
164 | bx lr\r | |
165 | \r | |
efda1775 | 166 | RVCT_ASM_EXPORT ArmWriteCpuActlr\r |
52d44f77 OM |
167 | mcr p15, 0, r0, c1, c0, 1\r |
168 | dsb\r | |
169 | isb\r | |
170 | bx lr\r | |
836c3500 | 171 | \r |
bd6b9799 | 172 | END\r |