Commit | Line | Data |
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3402aac7 | 1 | //------------------------------------------------------------------------------\r |
bd6b9799 | 2 | //\r |
3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
ff1f27c0 | 4 | // Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | //\r |
4059386c | 6 | // SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bd6b9799 | 7 | //\r |
8 | //------------------------------------------------------------------------------\r | |
9 | \r | |
bd6b9799 | 10 | INCLUDE AsmMacroIoLib.inc\r |
11 | \r | |
efda1775 EC |
12 | \r |
13 | INCLUDE AsmMacroExport.inc\r | |
14 | \r | |
15 | RVCT_ASM_EXPORT ArmReadMidr\r | |
bd6b9799 | 16 | mrc p15,0,R0,c0,c0,0\r |
17 | bx LR\r | |
18 | \r | |
efda1775 | 19 | RVCT_ASM_EXPORT ArmCacheInfo\r |
bd6b9799 | 20 | mrc p15,0,R0,c0,c0,1\r |
21 | bx LR\r | |
22 | \r | |
efda1775 | 23 | RVCT_ASM_EXPORT ArmGetInterruptState\r |
bd6b9799 | 24 | mrs R0,CPSR\r |
25 | tst R0,#0x80 // Check if IRQ is enabled.\r | |
26 | moveq R0,#1\r | |
27 | movne R0,#0\r | |
28 | bx LR\r | |
29 | \r | |
efda1775 | 30 | RVCT_ASM_EXPORT ArmGetFiqState\r |
bd6b9799 | 31 | mrs R0,CPSR\r |
32 | tst R0,#0x40 // Check if FIQ is enabled.\r | |
33 | moveq R0,#1\r | |
34 | movne R0,#0\r | |
35 | bx LR\r | |
36 | \r | |
efda1775 | 37 | RVCT_ASM_EXPORT ArmSetDomainAccessControl\r |
bd6b9799 | 38 | mcr p15,0,r0,c3,c0,0\r |
39 | bx lr\r | |
40 | \r | |
efda1775 | 41 | RVCT_ASM_EXPORT CPSRMaskInsert\r |
bd6b9799 | 42 | stmfd sp!, {r4-r12, lr} // save all the banked registers\r |
43 | mov r3, sp // copy the stack pointer into a non-banked register\r | |
44 | mrs r2, cpsr // read the cpsr\r | |
45 | bic r2, r2, r0 // clear mask in the cpsr\r | |
46 | and r1, r1, r0 // clear bits outside the mask in the input\r | |
47 | orr r2, r2, r1 // set field\r | |
48 | msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r | |
49 | isb\r | |
50 | mov sp, r3 // restore stack pointer\r | |
51 | ldmfd sp!, {r4-r12, lr} // restore registers\r | |
52 | bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r | |
53 | \r | |
efda1775 | 54 | RVCT_ASM_EXPORT CPSRRead\r |
bd6b9799 | 55 | mrs r0, cpsr\r |
56 | bx lr\r | |
57 | \r | |
efda1775 | 58 | RVCT_ASM_EXPORT ArmReadCpacr\r |
836c3500 | 59 | mrc p15, 0, r0, c1, c0, 2\r |
60 | bx lr\r | |
61 | \r | |
efda1775 | 62 | RVCT_ASM_EXPORT ArmWriteCpacr\r |
bd6b9799 | 63 | mcr p15, 0, r0, c1, c0, 2\r |
18029bb9 | 64 | isb\r |
bd6b9799 | 65 | bx lr\r |
66 | \r | |
efda1775 | 67 | RVCT_ASM_EXPORT ArmWriteAuxCr\r |
bd6b9799 | 68 | mcr p15, 0, r0, c1, c0, 1\r |
69 | bx lr\r | |
70 | \r | |
efda1775 | 71 | RVCT_ASM_EXPORT ArmReadAuxCr\r |
bd6b9799 | 72 | mrc p15, 0, r0, c1, c0, 1\r |
3402aac7 | 73 | bx lr\r |
bd6b9799 | 74 | \r |
efda1775 | 75 | RVCT_ASM_EXPORT ArmSetTTBR0\r |
bd6b9799 | 76 | mcr p15,0,r0,c2,c0,0\r |
77 | isb\r | |
78 | bx lr\r | |
79 | \r | |
ff1f27c0 EL |
80 | RVCT_ASM_EXPORT ArmSetTTBCR\r |
81 | mcr p15, 0, r0, c2, c0, 2\r | |
82 | isb\r | |
83 | bx lr\r | |
84 | \r | |
efda1775 | 85 | RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r |
bd6b9799 | 86 | mrc p15,0,r0,c2,c0,0\r |
0efaa42f | 87 | MOV32 r1, 0xFFFFC000\r |
bd6b9799 | 88 | and r0, r0, r1\r |
89 | isb\r | |
90 | bx lr\r | |
91 | \r | |
92 | //\r | |
93 | //VOID\r | |
94 | //ArmUpdateTranslationTableEntry (\r | |
95 | // IN VOID *TranslationTableEntry // R0\r | |
96 | // IN VOID *MVA // R1\r | |
97 | // );\r | |
efda1775 | 98 | RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r |
bd6b9799 | 99 | mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r |
100 | dsb\r | |
101 | mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r | |
102 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
103 | dsb\r | |
104 | isb\r | |
105 | bx lr\r | |
106 | \r | |
efda1775 | 107 | RVCT_ASM_EXPORT ArmInvalidateTlb\r |
bd6b9799 | 108 | mov r0,#0\r |
109 | mcr p15,0,r0,c8,c7,0\r | |
110 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
111 | dsb\r | |
112 | isb\r | |
113 | bx lr\r | |
114 | \r | |
efda1775 | 115 | RVCT_ASM_EXPORT ArmReadScr\r |
836c3500 | 116 | mrc p15, 0, r0, c1, c1, 0\r |
117 | bx lr\r | |
118 | \r | |
efda1775 | 119 | RVCT_ASM_EXPORT ArmWriteScr\r |
bd6b9799 | 120 | mcr p15, 0, r0, c1, c1, 0\r |
b2d0e0c5 | 121 | isb\r |
bd6b9799 | 122 | bx lr\r |
123 | \r | |
efda1775 | 124 | RVCT_ASM_EXPORT ArmReadHVBar\r |
5ea2c2d3 | 125 | mrc p15, 4, r0, c12, c0, 0\r |
126 | bx lr\r | |
127 | \r | |
efda1775 | 128 | RVCT_ASM_EXPORT ArmWriteHVBar\r |
5ea2c2d3 | 129 | mcr p15, 4, r0, c12, c0, 0\r |
130 | bx lr\r | |
131 | \r | |
efda1775 | 132 | RVCT_ASM_EXPORT ArmReadMVBar\r |
836c3500 | 133 | mrc p15, 0, r0, c12, c0, 1\r |
134 | bx lr\r | |
135 | \r | |
efda1775 | 136 | RVCT_ASM_EXPORT ArmWriteMVBar\r |
bd6b9799 | 137 | mcr p15, 0, r0, c12, c0, 1\r |
138 | bx lr\r | |
3402aac7 | 139 | \r |
efda1775 | 140 | RVCT_ASM_EXPORT ArmCallWFE\r |
b1d41be7 | 141 | wfe\r |
27995cd5 | 142 | bx lr\r |
b1d41be7 | 143 | \r |
efda1775 | 144 | RVCT_ASM_EXPORT ArmCallSEV\r |
b1d41be7 | 145 | sev\r |
27995cd5 | 146 | bx lr\r |
b1d41be7 | 147 | \r |
efda1775 | 148 | RVCT_ASM_EXPORT ArmReadSctlr\r |
27995cd5 | 149 | mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r |
91c38d4e | 150 | bx lr\r |
52d44f77 | 151 | \r |
1e1d1697 MZ |
152 | RVCT_ASM_EXPORT ArmWriteSctlr\r |
153 | mcr p15, 0, r0, c1, c0, 0\r | |
154 | bx lr\r | |
52d44f77 | 155 | \r |
efda1775 | 156 | RVCT_ASM_EXPORT ArmReadCpuActlr\r |
52d44f77 OM |
157 | mrc p15, 0, r0, c1, c0, 1\r |
158 | bx lr\r | |
159 | \r | |
efda1775 | 160 | RVCT_ASM_EXPORT ArmWriteCpuActlr\r |
52d44f77 OM |
161 | mcr p15, 0, r0, c1, c0, 1\r |
162 | dsb\r | |
163 | isb\r | |
164 | bx lr\r | |
836c3500 | 165 | \r |
95d04ebc AB |
166 | RVCT_ASM_EXPORT ArmGetPhysicalAddressBits\r |
167 | mrc p15, 0, r0, c0, c1, 4 ; MMFR0\r | |
168 | and r0, r0, #0xf ; VMSA [3:0]\r | |
169 | cmp r0, #5 ; >= 5 implies LPAE support\r | |
170 | movlt r0, #32 ; 32 bits if no LPAE\r | |
171 | movge r0, #40 ; 40 bits if LPAE\r | |
172 | bx lr\r | |
173 | \r | |
bd6b9799 | 174 | END\r |