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3402aac7 1#------------------------------------------------------------------------------\r
da9675a2 2#\r
3# Copyright (c) 2011, ARM Limited. All rights reserved.\r
0efaa42f 4# Copyright (c) 2016, Linaro Limited. All rights reserved.\r
da9675a2 5#\r
4059386c 6# SPDX-License-Identifier: BSD-2-Clause-Patent\r
da9675a2 7#\r
8#------------------------------------------------------------------------------\r
9\r
0efaa42f
AB
10#include <AsmMacroIoLib.h>\r
11\r
12ASM_FUNC(ArmReadCntFrq)\r
da9675a2 13 mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ\r
14 bx lr\r
15\r
0efaa42f 16ASM_FUNC(ArmWriteCntFrq)\r
da9675a2 17 mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ\r
18 bx lr\r
19\r
0efaa42f 20ASM_FUNC(ArmReadCntPct)\r
da9675a2 21 mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)\r
22 bx lr\r
23\r
0efaa42f 24ASM_FUNC(ArmReadCntkCtl)\r
da9675a2 25 mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)\r
26 bx lr\r
27\r
0efaa42f 28ASM_FUNC(ArmWriteCntkCtl)\r
da9675a2 29 mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)\r
30 bx lr\r
31\r
0efaa42f 32ASM_FUNC(ArmReadCntpTval)\r
da9675a2 33 mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)\r
34 bx lr\r
35\r
0efaa42f 36ASM_FUNC(ArmWriteCntpTval)\r
da9675a2 37 mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)\r
38 bx lr\r
39\r
0efaa42f 40ASM_FUNC(ArmReadCntpCtl)\r
da9675a2 41 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)\r
42 bx lr\r
43\r
0efaa42f 44ASM_FUNC(ArmWriteCntpCtl)\r
da9675a2 45 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)\r
46 bx lr\r
47\r
0efaa42f 48ASM_FUNC(ArmReadCntvTval)\r
da9675a2 49 mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)\r
50 bx lr\r
51\r
0efaa42f 52ASM_FUNC(ArmWriteCntvTval)\r
da9675a2 53 mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)\r
54 bx lr\r
55\r
0efaa42f 56ASM_FUNC(ArmReadCntvCtl)\r
da9675a2 57 mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)\r
58 bx lr\r
59\r
0efaa42f 60ASM_FUNC(ArmWriteCntvCtl)\r
da9675a2 61 mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)\r
62 bx lr\r
63\r
0efaa42f 64ASM_FUNC(ArmReadCntvCt)\r
da9675a2 65 mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)\r
66 bx lr\r
67\r
0efaa42f 68ASM_FUNC(ArmReadCntpCval)\r
da9675a2 69 mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)\r
70 bx lr\r
71\r
0efaa42f 72ASM_FUNC(ArmWriteCntpCval)\r
da9675a2 73 mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)\r
74 bx lr\r
75\r
0efaa42f 76ASM_FUNC(ArmReadCntvCval)\r
da9675a2 77 mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)\r
78 bx lr\r
79\r
0efaa42f 80ASM_FUNC(ArmWriteCntvCval)\r
da9675a2 81 mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)\r
82 bx lr\r
83\r
0efaa42f 84ASM_FUNC(ArmReadCntvOff)\r
da9675a2 85 mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)\r
86 bx lr\r
87\r
0efaa42f 88ASM_FUNC(ArmWriteCntvOff)\r
da9675a2 89 mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)\r
90 bx lr\r
91\r
92ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r