projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3402aac7 | 1 | #------------------------------------------------------------------------------\r |
| bd6b9799 | 2 | #\r |
| 3 | # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
| 9401d6f4 | 4 | # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
| 0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
| bd6b9799 | 6 | #\r |
| 4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| bd6b9799 | 8 | #\r |
| 9 | #------------------------------------------------------------------------------\r | |
| 10 | \r | |
| 0efaa42f | 11 | #include <AsmMacroIoLib.h>\r |
| bd6b9799 | 12 | \r |
| 13 | .set DC_ON, (0x1<<2)\r | |
| 14 | .set IC_ON, (0x1<<12)\r | |
| 15 | .set CTRL_M_BIT, (1 << 0)\r | |
| 16 | .set CTRL_C_BIT, (1 << 2)\r | |
| 17 | .set CTRL_B_BIT, (1 << 7)\r | |
| 18 | .set CTRL_I_BIT, (1 << 12)\r | |
| 19 | \r | |
| 20 | \r | |
| 0efaa42f | 21 | ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r |
| 3402aac7 | 22 | mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r |
| bd6b9799 | 23 | bx lr\r |
| 24 | \r | |
| 0efaa42f | 25 | ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r |
| 3402aac7 | 26 | mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r |
| bd6b9799 | 27 | bx lr\r |
| 28 | \r | |
| 29 | \r | |
| 0efaa42f | 30 | ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r |
| b7de7e3c EC |
31 | mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU\r |
| 32 | bx lr\r | |
| 33 | \r | |
| 0efaa42f | 34 | ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r |
| cf580da1 AB |
35 | mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU\r |
| 36 | mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor\r | |
| 37 | bx lr\r | |
| b7de7e3c | 38 | \r |
| 0efaa42f | 39 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r |
| bd6b9799 | 40 | mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r |
| bd6b9799 | 41 | bx lr\r |
| 42 | \r | |
| 43 | \r | |
| 0efaa42f | 44 | ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r |
| 3402aac7 | 45 | mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\r |
| bd6b9799 | 46 | bx lr\r |
| 47 | \r | |
| 48 | \r | |
| 0efaa42f | 49 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r |
| 3402aac7 | 50 | mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\r |
| bd6b9799 | 51 | bx lr\r |
| 52 | \r | |
| 53 | \r | |
| 0efaa42f | 54 | ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r |
| 3402aac7 | 55 | mcr p15, 0, r0, c7, c10, 2 @ Clean this line\r |
| bd6b9799 | 56 | bx lr\r |
| 57 | \r | |
| 0efaa42f | 58 | ASM_FUNC(ArmInvalidateInstructionCache)\r |
| bd6b9799 | 59 | mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache\r |
| 60 | dsb\r | |
| 61 | isb\r | |
| 62 | bx LR\r | |
| 63 | \r | |
| 0efaa42f | 64 | ASM_FUNC(ArmEnableMmu)\r |
| bd6b9799 | 65 | mrc p15,0,R0,c1,c0,0\r |
| 66 | orr R0,R0,#1\r | |
| 67 | mcr p15,0,R0,c1,c0,0\r | |
| 68 | dsb\r | |
| 69 | isb\r | |
| 70 | bx LR\r | |
| 71 | \r | |
| 72 | \r | |
| 0efaa42f | 73 | ASM_FUNC(ArmDisableMmu)\r |
| bd6b9799 | 74 | mrc p15,0,R0,c1,c0,0\r |
| 75 | bic R0,R0,#1\r | |
| 76 | mcr p15,0,R0,c1,c0,0 @Disable MMU\r | |
| 77 | \r | |
| 78 | mcr p15,0,R0,c8,c7,0 @Invalidate TLB\r | |
| 79 | mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array\r | |
| 80 | dsb\r | |
| 81 | isb\r | |
| 82 | bx LR\r | |
| 83 | \r | |
| 0efaa42f | 84 | ASM_FUNC(ArmDisableCachesAndMmu)\r |
| bd6b9799 | 85 | mrc p15, 0, r0, c1, c0, 0 @ Get control register\r |
| 86 | bic r0, r0, #CTRL_M_BIT @ Disable MMU\r | |
| 87 | bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r | |
| 88 | bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r | |
| 89 | mcr p15, 0, r0, c1, c0, 0 @ Write control register\r | |
| 90 | dsb\r | |
| 91 | isb\r | |
| 92 | bx LR\r | |
| 93 | \r | |
| 0efaa42f | 94 | ASM_FUNC(ArmMmuEnabled)\r |
| bd6b9799 | 95 | mrc p15,0,R0,c1,c0,0\r |
| 96 | and R0,R0,#1\r | |
| 3402aac7 | 97 | bx LR\r |
| bd6b9799 | 98 | \r |
| 0efaa42f | 99 | ASM_FUNC(ArmEnableDataCache)\r |
| bd6b9799 | 100 | ldr R1,=DC_ON\r |
| 101 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
| 102 | orr R0,R0,R1 @Set C bit\r | |
| 103 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
| 104 | dsb\r | |
| 105 | isb\r | |
| 106 | bx LR\r | |
| 3402aac7 | 107 | \r |
| 0efaa42f | 108 | ASM_FUNC(ArmDisableDataCache)\r |
| bd6b9799 | 109 | ldr R1,=DC_ON\r |
| 110 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
| 111 | bic R0,R0,R1 @Clear C bit\r | |
| 112 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
| 113 | dsb\r | |
| 114 | isb\r | |
| 115 | bx LR\r | |
| 116 | \r | |
| 0efaa42f | 117 | ASM_FUNC(ArmEnableInstructionCache)\r |
| bd6b9799 | 118 | ldr R1,=IC_ON\r |
| 119 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
| 120 | orr R0,R0,R1 @Set I bit\r | |
| 121 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
| 122 | dsb\r | |
| 123 | isb\r | |
| 124 | bx LR\r | |
| 3402aac7 | 125 | \r |
| 0efaa42f | 126 | ASM_FUNC(ArmDisableInstructionCache)\r |
| bd6b9799 | 127 | ldr R1,=IC_ON\r |
| 128 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
| 129 | bic R0,R0,R1 @Clear I bit.\r | |
| 130 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
| 131 | dsb\r | |
| 132 | isb\r | |
| 133 | bx LR\r | |
| 134 | \r | |
| 0efaa42f | 135 | ASM_FUNC(ArmEnableSWPInstruction)\r |
| bd6b9799 | 136 | mrc p15, 0, r0, c1, c0, 0\r |
| 137 | orr r0, r0, #0x00000400\r | |
| 138 | mcr p15, 0, r0, c1, c0, 0\r | |
| 139 | isb\r | |
| 140 | bx LR\r | |
| 141 | \r | |
| 0efaa42f | 142 | ASM_FUNC(ArmEnableBranchPrediction)\r |
| bd6b9799 | 143 | mrc p15, 0, r0, c1, c0, 0\r |
| 144 | orr r0, r0, #0x00000800\r | |
| 145 | mcr p15, 0, r0, c1, c0, 0\r | |
| 146 | dsb\r | |
| 147 | isb\r | |
| 148 | bx LR\r | |
| 149 | \r | |
| 0efaa42f | 150 | ASM_FUNC(ArmDisableBranchPrediction)\r |
| bd6b9799 | 151 | mrc p15, 0, r0, c1, c0, 0\r |
| 152 | bic r0, r0, #0x00000800\r | |
| 153 | mcr p15, 0, r0, c1, c0, 0\r | |
| 154 | dsb\r | |
| 155 | isb\r | |
| 156 | bx LR\r | |
| 157 | \r | |
| 0efaa42f | 158 | ASM_FUNC(ArmSetLowVectors)\r |
| bd6b9799 | 159 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r |
| 160 | bic r0, r0, #0x00002000 @ clear V bit\r | |
| 161 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r | |
| 162 | isb\r | |
| 163 | bx LR\r | |
| 164 | \r | |
| 0efaa42f | 165 | ASM_FUNC(ArmSetHighVectors)\r |
| bd6b9799 | 166 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r |
| c6ba1c12 | 167 | orr r0, r0, #0x00002000 @ Set V bit\r |
| bd6b9799 | 168 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r |
| 169 | isb\r | |
| 170 | bx LR\r | |
| 171 | \r | |
| 0efaa42f | 172 | ASM_FUNC(ArmV7AllDataCachesOperation)\r |
| bd6b9799 | 173 | stmfd SP!,{r4-r12, LR}\r |
| 174 | mov R1, R0 @ Save Function call in R1\r | |
| 175 | mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r | |
| 176 | ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)\r | |
| 177 | mov R3, R3, LSR #23 @ Cache level value (naturally aligned)\r | |
| 178 | beq L_Finished\r | |
| 179 | mov R10, #0\r | |
| 180 | \r | |
| 3402aac7 | 181 | Loop1:\r |
| bd6b9799 | 182 | add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r |
| 183 | mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r | |
| 184 | and R12, R12, #7 @ get those 3 bits alone\r | |
| 185 | cmp R12, #2\r | |
| 186 | blt L_Skip @ no cache or only instruction cache at this level\r | |
| 187 | mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r | |
| 3402aac7 | 188 | isb @ isb to sync the change to the CacheSizeID reg\r |
| bd6b9799 | 189 | mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r |
| 190 | and R2, R12, #0x7 @ extract the line length field\r | |
| 191 | add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r | |
| 192 | @ ldr R4, =0x3FF\r | |
| 193 | mov R4, #0x400\r | |
| 194 | sub R4, R4, #1\r | |
| 195 | ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r | |
| 196 | clz R5, R4 @ R5 is the bit position of the way size increment\r | |
| 197 | @ ldr R7, =0x00007FFF\r | |
| 198 | mov R7, #0x00008000\r | |
| 199 | sub R7, R7, #1\r | |
| 200 | ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r | |
| 201 | \r | |
| 3402aac7 | 202 | Loop2:\r |
| bd6b9799 | 203 | mov R9, R4 @ R9 working copy of the max way size (right aligned)\r |
| 204 | \r | |
| 3402aac7 | 205 | Loop3:\r |
| bd6b9799 | 206 | orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r |
| 207 | orr R0, R0, R7, LSL R2 @ factor in the index number\r | |
| 208 | \r | |
| 209 | blx R1\r | |
| 210 | \r | |
| 211 | subs R9, R9, #1 @ decrement the way number\r | |
| 212 | bge Loop3\r | |
| 213 | subs R7, R7, #1 @ decrement the index\r | |
| 214 | bge Loop2\r | |
| 3402aac7 | 215 | L_Skip:\r |
| bd6b9799 | 216 | add R10, R10, #2 @ increment the cache number\r |
| 217 | cmp R3, R10\r | |
| 218 | bgt Loop1\r | |
| 3402aac7 | 219 | \r |
| bd6b9799 | 220 | L_Finished:\r |
| 221 | dsb\r | |
| 222 | ldmfd SP!, {r4-r12, lr}\r | |
| 223 | bx LR\r | |
| 224 | \r | |
| 0efaa42f | 225 | ASM_FUNC(ArmDataMemoryBarrier)\r |
| bd6b9799 | 226 | dmb\r |
| 227 | bx LR\r | |
| 3402aac7 | 228 | \r |
| 0efaa42f | 229 | ASM_FUNC(ArmDataSynchronizationBarrier)\r |
| bd6b9799 | 230 | dsb\r |
| 231 | bx LR\r | |
| 3402aac7 | 232 | \r |
| 0efaa42f | 233 | ASM_FUNC(ArmInstructionSynchronizationBarrier)\r |
| bd6b9799 | 234 | isb\r |
| 235 | bx LR\r | |
| 236 | \r | |
| 0efaa42f | 237 | ASM_FUNC(ArmReadVBar)\r |
| 836c3500 | 238 | # Set the Address of the Vector Table in the VBAR register\r |
| 239 | mrc p15, 0, r0, c12, c0, 0\r | |
| 240 | bx lr\r | |
| 241 | \r | |
| 0efaa42f | 242 | ASM_FUNC(ArmWriteVBar)\r |
| bd6b9799 | 243 | # Set the Address of the Vector Table in the VBAR register\r |
| 3402aac7 | 244 | mcr p15, 0, r0, c12, c0, 0\r |
| bd6b9799 | 245 | # Ensure the SCTLR.V bit is clear\r |
| 246 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r | |
| 247 | bic r0, r0, #0x00002000 @ clear V bit\r | |
| 248 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r | |
| 249 | isb\r | |
| 250 | bx lr\r | |
| 251 | \r | |
| 0efaa42f | 252 | ASM_FUNC(ArmEnableVFP)\r |
| bd6b9799 | 253 | # Read CPACR (Coprocessor Access Control Register)\r |
| 254 | mrc p15, 0, r0, c1, c0, 2\r | |
| 255 | # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r | |
| 256 | orr r0, r0, #0x00f00000\r | |
| 257 | # Write back CPACR (Coprocessor Access Control Register)\r | |
| 258 | mcr p15, 0, r0, c1, c0, 2\r | |
| 18029bb9 | 259 | isb\r |
| bd6b9799 | 260 | # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r |
| 261 | mov r0, #0x40000000\r | |
| 6d2449c1 | 262 | #ifndef __clang__\r |
| bd6b9799 | 263 | mcr p10,#0x7,r0,c8,c0,#0\r |
| 6d2449c1 AB |
264 | #else\r |
| 265 | vmsr fpexc, r0\r | |
| 266 | #endif\r | |
| bd6b9799 | 267 | bx lr\r |
| 268 | \r | |
| 0efaa42f | 269 | ASM_FUNC(ArmCallWFI)\r |
| bd6b9799 | 270 | wfi\r |
| 271 | bx lr\r | |
| 272 | \r | |
| 273 | #Note: Return 0 in Uniprocessor implementation\r | |
| 0efaa42f | 274 | ASM_FUNC(ArmReadCbar)\r |
| bd6b9799 | 275 | mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register\r |
| 276 | bx lr\r | |
| 277 | \r | |
| 0efaa42f | 278 | ASM_FUNC(ArmReadMpidr)\r |
| bd6b9799 | 279 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r |
| 280 | bx lr\r | |
| 3402aac7 | 281 | \r |
| 0efaa42f | 282 | ASM_FUNC(ArmReadTpidrurw)\r |
| bd6b9799 | 283 | mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r |
| 284 | bx lr\r | |
| 285 | \r | |
| 0efaa42f | 286 | ASM_FUNC(ArmWriteTpidrurw)\r |
| bd6b9799 | 287 | mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW\r |
| 288 | bx lr\r | |
| 289 | \r | |
| 0efaa42f | 290 | ASM_FUNC(ArmIsArchTimerImplemented)\r |
| bd6b9799 | 291 | mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1\r |
| 292 | and r0, r0, #0x000F0000\r | |
| 293 | bx lr\r | |
| 294 | \r | |
| 0efaa42f | 295 | ASM_FUNC(ArmReadIdPfr1)\r |
| bd6b9799 | 296 | mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r |
| 297 | bx lr\r | |
| 298 | \r | |
| 299 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |