Commit | Line | Data |
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3402aac7 | 1 | //------------------------------------------------------------------------------\r |
bd6b9799 | 2 | //\r |
3 | // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
9401d6f4 | 4 | // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | //\r |
4059386c | 6 | // SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bd6b9799 | 7 | //\r |
8 | //------------------------------------------------------------------------------\r | |
9 | \r | |
efda1775 EC |
10 | \r |
11 | INCLUDE AsmMacroExport.inc\r | |
bd6b9799 | 12 | PRESERVE8\r |
13 | \r | |
14 | DC_ON EQU ( 0x1:SHL:2 )\r | |
15 | IC_ON EQU ( 0x1:SHL:12 )\r | |
16 | CTRL_M_BIT EQU (1 << 0)\r | |
17 | CTRL_C_BIT EQU (1 << 2)\r | |
18 | CTRL_B_BIT EQU (1 << 7)\r | |
19 | CTRL_I_BIT EQU (1 << 12)\r | |
20 | \r | |
21 | \r | |
efda1775 | 22 | RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r |
3402aac7 | 23 | mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r |
bd6b9799 | 24 | bx lr\r |
25 | \r | |
efda1775 | 26 | RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r |
3402aac7 | 27 | mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r |
bd6b9799 | 28 | bx lr\r |
29 | \r | |
30 | \r | |
cf580da1 AB |
31 | RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA\r |
32 | mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU\r | |
33 | mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor\r | |
34 | bx lr\r | |
35 | \r | |
36 | \r | |
b7de7e3c EC |
37 | RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r |
38 | mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU\r | |
39 | bx lr\r | |
40 | \r | |
41 | \r | |
efda1775 | 42 | RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r |
bd6b9799 | 43 | mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r |
bd6b9799 | 44 | bx lr\r |
45 | \r | |
46 | \r | |
efda1775 | 47 | RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r |
3402aac7 | 48 | mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r |
bd6b9799 | 49 | bx lr\r |
50 | \r | |
51 | \r | |
efda1775 | 52 | RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r |
3402aac7 | 53 | mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r |
bd6b9799 | 54 | bx lr\r |
55 | \r | |
56 | \r | |
efda1775 | 57 | RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r |
3402aac7 | 58 | mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r |
bd6b9799 | 59 | bx lr\r |
60 | \r | |
61 | \r | |
efda1775 | 62 | RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r |
bd6b9799 | 63 | mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r |
64 | isb\r | |
65 | bx LR\r | |
66 | \r | |
efda1775 | 67 | RVCT_ASM_EXPORT ArmEnableMmu\r |
bd6b9799 | 68 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r |
69 | orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r | |
70 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
71 | dsb\r | |
72 | isb\r | |
73 | bx LR\r | |
74 | \r | |
efda1775 | 75 | RVCT_ASM_EXPORT ArmDisableMmu\r |
bd6b9799 | 76 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r |
77 | bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r | |
78 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
79 | \r | |
80 | mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r | |
81 | mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r | |
82 | dsb\r | |
83 | isb\r | |
84 | bx LR\r | |
85 | \r | |
efda1775 | 86 | RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r |
bd6b9799 | 87 | mrc p15, 0, r0, c1, c0, 0 ; Get control register\r |
88 | bic r0, r0, #CTRL_M_BIT ; Disable MMU\r | |
89 | bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r | |
90 | bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r | |
91 | mcr p15, 0, r0, c1, c0, 0 ; Write control register\r | |
92 | dsb\r | |
93 | isb\r | |
94 | bx LR\r | |
95 | \r | |
efda1775 | 96 | RVCT_ASM_EXPORT ArmMmuEnabled\r |
bd6b9799 | 97 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r |
98 | and R0,R0,#1\r | |
99 | bx LR\r | |
100 | \r | |
efda1775 | 101 | RVCT_ASM_EXPORT ArmEnableDataCache\r |
bd6b9799 | 102 | ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r |
103 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
104 | orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r | |
105 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
106 | dsb\r | |
107 | isb\r | |
108 | bx LR\r | |
3402aac7 | 109 | \r |
efda1775 | 110 | RVCT_ASM_EXPORT ArmDisableDataCache\r |
bd6b9799 | 111 | ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r |
112 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
113 | bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r | |
114 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
115 | dsb\r | |
116 | isb\r | |
117 | bx LR\r | |
118 | \r | |
efda1775 | 119 | RVCT_ASM_EXPORT ArmEnableInstructionCache\r |
bd6b9799 | 120 | ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r |
121 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
122 | orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r | |
123 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
124 | dsb\r | |
125 | isb\r | |
126 | bx LR\r | |
3402aac7 | 127 | \r |
efda1775 | 128 | RVCT_ASM_EXPORT ArmDisableInstructionCache\r |
bd6b9799 | 129 | ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r |
130 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
131 | BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r | |
132 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
133 | isb\r | |
134 | bx LR\r | |
135 | \r | |
efda1775 | 136 | RVCT_ASM_EXPORT ArmEnableSWPInstruction\r |
bd6b9799 | 137 | mrc p15, 0, r0, c1, c0, 0\r |
138 | orr r0, r0, #0x00000400\r | |
139 | mcr p15, 0, r0, c1, c0, 0\r | |
140 | isb\r | |
141 | bx LR\r | |
142 | \r | |
efda1775 | 143 | RVCT_ASM_EXPORT ArmEnableBranchPrediction\r |
bd6b9799 | 144 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
145 | orr r0, r0, #0x00000800 ;\r | |
146 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
147 | dsb\r | |
148 | isb\r | |
149 | bx LR\r | |
150 | \r | |
efda1775 | 151 | RVCT_ASM_EXPORT ArmDisableBranchPrediction\r |
bd6b9799 | 152 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
153 | bic r0, r0, #0x00000800 ;\r | |
154 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
155 | dsb\r | |
156 | isb\r | |
157 | bx LR\r | |
158 | \r | |
efda1775 | 159 | RVCT_ASM_EXPORT ArmSetLowVectors\r |
bd6b9799 | 160 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
161 | bic r0, r0, #0x00002000 ; clear V bit\r | |
162 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
163 | isb\r | |
164 | bx LR\r | |
165 | \r | |
efda1775 | 166 | RVCT_ASM_EXPORT ArmSetHighVectors\r |
bd6b9799 | 167 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
c6ba1c12 | 168 | orr r0, r0, #0x00002000 ; Set V bit\r |
bd6b9799 | 169 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r |
170 | isb\r | |
171 | bx LR\r | |
172 | \r | |
efda1775 | 173 | RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r |
bd6b9799 | 174 | stmfd SP!,{r4-r12, LR}\r |
175 | mov R1, R0 ; Save Function call in R1\r | |
176 | mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r | |
177 | ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r | |
178 | mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r | |
179 | beq Finished\r | |
180 | mov R10, #0\r | |
181 | \r | |
3402aac7 | 182 | Loop1\r |
bd6b9799 | 183 | add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r |
184 | mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r | |
185 | and R12, R12, #7 ; get those 3 bits alone\r | |
186 | cmp R12, #2\r | |
187 | blt Skip ; no cache or only instruction cache at this level\r | |
188 | mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r | |
3402aac7 | 189 | isb ; isb to sync the change to the CacheSizeID reg\r |
bd6b9799 | 190 | mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r |
191 | and R2, R12, #&7 ; extract the line length field\r | |
192 | add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r | |
193 | ldr R4, =0x3FF\r | |
194 | ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r | |
195 | clz R5, R4 ; R5 is the bit position of the way size increment\r | |
196 | ldr R7, =0x00007FFF\r | |
197 | ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r | |
198 | \r | |
3402aac7 | 199 | Loop2\r |
bd6b9799 | 200 | mov R9, R4 ; R9 working copy of the max way size (right aligned)\r |
201 | \r | |
3402aac7 | 202 | Loop3\r |
bd6b9799 | 203 | orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r |
204 | orr R0, R0, R7, LSL R2 ; factor in the index number\r | |
205 | \r | |
206 | blx R1\r | |
207 | \r | |
208 | subs R9, R9, #1 ; decrement the way number\r | |
209 | bge Loop3\r | |
210 | subs R7, R7, #1 ; decrement the index\r | |
211 | bge Loop2\r | |
3402aac7 | 212 | Skip\r |
bd6b9799 | 213 | add R10, R10, #2 ; increment the cache number\r |
214 | cmp R3, R10\r | |
215 | bgt Loop1\r | |
3402aac7 | 216 | \r |
bd6b9799 | 217 | Finished\r |
218 | dsb\r | |
219 | ldmfd SP!, {r4-r12, lr}\r | |
220 | bx LR\r | |
221 | \r | |
efda1775 | 222 | RVCT_ASM_EXPORT ArmDataMemoryBarrier\r |
bd6b9799 | 223 | dmb\r |
224 | bx LR\r | |
3402aac7 | 225 | \r |
efda1775 | 226 | RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r |
bd6b9799 | 227 | dsb\r |
228 | bx LR\r | |
3402aac7 | 229 | \r |
efda1775 | 230 | RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r |
bd6b9799 | 231 | isb\r |
232 | bx LR\r | |
233 | \r | |
efda1775 | 234 | RVCT_ASM_EXPORT ArmReadVBar\r |
836c3500 | 235 | // Set the Address of the Vector Table in the VBAR register\r |
236 | mrc p15, 0, r0, c12, c0, 0\r | |
237 | bx lr\r | |
238 | \r | |
efda1775 | 239 | RVCT_ASM_EXPORT ArmWriteVBar\r |
bd6b9799 | 240 | // Set the Address of the Vector Table in the VBAR register\r |
3402aac7 | 241 | mcr p15, 0, r0, c12, c0, 0\r |
bd6b9799 | 242 | // Ensure the SCTLR.V bit is clear\r |
243 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
244 | bic r0, r0, #0x00002000 ; clear V bit\r | |
245 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
246 | isb\r | |
247 | bx lr\r | |
248 | \r | |
efda1775 | 249 | RVCT_ASM_EXPORT ArmEnableVFP\r |
bd6b9799 | 250 | // Read CPACR (Coprocessor Access Control Register)\r |
251 | mrc p15, 0, r0, c1, c0, 2\r | |
252 | // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r | |
253 | orr r0, r0, #0x00f00000\r | |
254 | // Write back CPACR (Coprocessor Access Control Register)\r | |
255 | mcr p15, 0, r0, c1, c0, 2\r | |
18029bb9 | 256 | isb\r |
bd6b9799 | 257 | // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r |
258 | mov r0, #0x40000000\r | |
259 | mcr p10,#0x7,r0,c8,c0,#0\r | |
260 | bx lr\r | |
261 | \r | |
efda1775 | 262 | RVCT_ASM_EXPORT ArmCallWFI\r |
bd6b9799 | 263 | wfi\r |
264 | bx lr\r | |
265 | \r | |
266 | //Note: Return 0 in Uniprocessor implementation\r | |
efda1775 | 267 | RVCT_ASM_EXPORT ArmReadCbar\r |
bd6b9799 | 268 | mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r |
269 | bx lr\r | |
270 | \r | |
efda1775 | 271 | RVCT_ASM_EXPORT ArmReadMpidr\r |
bd6b9799 | 272 | mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r |
273 | bx lr\r | |
274 | \r | |
efda1775 | 275 | RVCT_ASM_EXPORT ArmReadTpidrurw\r |
bd6b9799 | 276 | mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r |
277 | bx lr\r | |
278 | \r | |
efda1775 | 279 | RVCT_ASM_EXPORT ArmWriteTpidrurw\r |
bd6b9799 | 280 | mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r |
281 | bx lr\r | |
282 | \r | |
efda1775 | 283 | RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r |
bd6b9799 | 284 | mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r |
285 | and r0, r0, #0x000F0000\r | |
286 | bx lr\r | |
287 | \r | |
efda1775 | 288 | RVCT_ASM_EXPORT ArmReadIdPfr1\r |
bd6b9799 | 289 | mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r |
290 | bx lr\r | |
291 | \r | |
292 | END\r |