[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm11 / Arm11Support.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <AsmMacroIoLib.h>\r
\r
.text\r
.align 2\r
GCC_ASM_EXPORT(ArmDisableCachesAndMmu)\r
GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r
GCC_ASM_EXPORT(ArmCleanDataCache)\r
GCC_ASM_EXPORT(ArmInvalidateDataCache)\r
GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r
GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r
GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r
GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r
GCC_ASM_EXPORT(ArmEnableMmu)\r
GCC_ASM_EXPORT(ArmDisableMmu)\r
GCC_ASM_EXPORT(ArmMmuEnabled)\r
GCC_ASM_EXPORT(ArmEnableDataCache)\r
GCC_ASM_EXPORT(ArmDisableDataCache)\r
GCC_ASM_EXPORT(ArmEnableInstructionCache)\r
GCC_ASM_EXPORT(ArmDisableInstructionCache)\r
GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r
GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r
GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r
GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r
GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r
GCC_ASM_EXPORT(ArmSetLowVectors)\r
GCC_ASM_EXPORT(ArmSetHighVectors)\r
GCC_ASM_EXPORT(ArmIsMpCore)\r
GCC_ASM_EXPORT(ArmCallWFI)\r
GCC_ASM_EXPORT(ArmReadMpidr)\r
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
GCC_ASM_EXPORT(ArmEnableFiq)\r
GCC_ASM_EXPORT(ArmDisableFiq)\r
GCC_ASM_EXPORT(ArmEnableInterrupts)\r
GCC_ASM_EXPORT(ArmDisableInterrupts)\r
GCC_ASM_EXPORT (ArmEnableVFP)\r
\r
Arm11PartNumberMask:  .word       0xFFF0\r
Arm11PartNumber:      .word	      0xB020\r
\r
.set DC_ON, (0x1<<2)\r
.set IC_ON, (0x1<<12)\r
.set XP_ON, (0x1<<23)\r
.set CTRL_M_BIT,  (1 << 0)\r
.set CTRL_C_BIT,  (1 << 2)\r
.set CTRL_I_BIT,  (1 << 12)\r
\r
ASM_PFX(ArmDisableCachesAndMmu):\r
  mrc   p15, 0, r0, c1, c0, 0           @ Get control register\r
  bic   r0, r0, #CTRL_M_BIT             @ Disable MMU\r
  bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache\r
  bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache\r
  mcr   p15, 0, r0, c1, c0, 0           @ Write control register\r
  bx      LR\r
\r
ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
  mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB\r
  bx lr\r
\r
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line\r
  bx      lr\r
\r
\r
ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line\r
  bx      lr\r
\r
\r
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line\r
  bx      lr\r
\r
\r
ASM_PFX(ArmCleanDataCache):\r
  mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache\r
  bx      lr\r
\r
\r
ASM_PFX(ArmCleanInvalidateDataCache):\r
  mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache\r
  bx      lr\r
\r
\r
ASM_PFX(ArmInvalidateDataCache):\r
  mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache\r
  bx      lr\r
\r
\r
ASM_PFX(ArmInvalidateInstructionCache):\r
  mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache\r
  mov     R0,#0\r
  mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer\r
  bx      lr\r
\r
ASM_PFX(ArmEnableMmu):\r
  mrc     p15,0,R0,c1,c0,0\r
  orr     R0,R0,#1\r
  mcr     p15,0,R0,c1,c0,0\r
  bx      LR\r
\r
ASM_PFX(ArmMmuEnabled):\r
  mrc     p15,0,R0,c1,c0,0\r
  and     R0,R0,#1\r
  bx      LR\r
\r
ASM_PFX(ArmDisableMmu):\r
  mrc     p15,0,R0,c1,c0,0\r
  bic     R0,R0,#1\r
  mcr     p15,0,R0,c1,c0,0\r
  mov     R0,#0\r
  mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier\r
  mov     R0,#0\r
  mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer\r
  bx      LR\r
\r
ASM_PFX(ArmEnableDataCache):\r
  LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON\r
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
  orr     R0,R0,R1              @Set C bit\r
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data\r
  bx      LR\r
\r
ASM_PFX(ArmDisableDataCache):\r
  LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON\r
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
  bic     R0,R0,R1              @Clear C bit\r
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data\r
  bx      LR\r
\r
ASM_PFX(ArmEnableInstructionCache):\r
  ldr     R1,=IC_ON\r
  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data\r
  orr     R0,R0,R1             @Set I bit\r
  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data\r
  bx      LR\r
\r
ASM_PFX(ArmDisableInstructionCache):\r
  ldr     R1,=IC_ON\r
  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data\r
  bic     R0,R0,R1             @Clear I bit.\r
  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data\r
  bx      LR\r
\r
ASM_PFX(ArmEnableBranchPrediction):\r
  mrc     p15, 0, r0, c1, c0, 0\r
  orr     r0, r0, #0x00000800\r
  mcr     p15, 0, r0, c1, c0, 0\r
  bx      LR\r
\r
ASM_PFX(ArmDisableBranchPrediction):\r
  mrc     p15, 0, r0, c1, c0, 0\r
  bic     r0, r0, #0x00000800\r
  mcr     p15, 0, r0, c1, c0, 0\r
  bx      LR\r
\r
ASM_PFX(ArmDataMemoryBarrier):\r
  mov R0, #0\r
  mcr P15, #0, R0, C7, C10, #5\r
  bx      LR\r
\r
ASM_PFX(ArmDataSyncronizationBarrier):\r
  mov R0, #0\r
  mcr P15, #0, R0, C7, C10, #4\r
  bx      LR\r
\r
ASM_PFX(ArmInstructionSynchronizationBarrier):\r
  mov R0, #0\r
  mcr P15, #0, R0, C7, C5, #4\r
  bx      LR\r
\r
ASM_PFX(ArmSetLowVectors):\r
  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   @ clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
  bx      LR\r
\r
ASM_PFX(ArmSetHighVectors):\r
  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00002000   @ clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
  bx      LR\r
\r
ASM_PFX(ArmIsMpCore):\r
  push    { r1 }\r
  mrc     p15, 0, r0, c0, c0, 0\r
  # Extract Part Number to check it is an ARM11MP core (0xB02)\r
  LoadConstantToReg (Arm11PartNumberMask, r1)\r
  and     r0, r0, r1\r
  LoadConstantToReg (Arm11PartNumber, r1)\r
  cmp     r0, r1\r
  movne   r0, #0\r
  pop     { r1 }\r
  bx      lr\r
\r
ASM_PFX(ArmCallWFI):\r
  wfi\r
  bx      lr\r
\r
ASM_PFX(ArmReadMpidr):\r
  mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR\r
  bx      lr\r
\r
ASM_PFX(ArmEnableFiq):\r
  mrs     R0,CPSR\r
  bic     R0,R0,#0x40    @Enable FIQ interrupts\r
  msr     CPSR_c,R0\r
  bx      LR\r
\r
ASM_PFX(ArmDisableFiq):\r
  mrs     R0,CPSR\r
  orr     R1,R0,#0x40    @Disable FIQ interrupts\r
  msr     CPSR_c,R1\r
  tst     R0,#0x80\r
  moveq   R0,#1\r
  movne   R0,#0\r
  bx      LR\r
\r
ASM_PFX(ArmEnableInterrupts):\r
  mrs     R0,CPSR\r
  bic     R0,R0,#0x80    @Enable IRQ interrupts\r
  msr     CPSR_c,R0\r
  bx      LR\r
\r
ASM_PFX(ArmDisableInterrupts):\r
  mrs     R0,CPSR\r
  orr     R1,R0,#0x80    @Disable IRQ interrupts\r
  msr     CPSR_c,R1\r
  tst     R0,#0x80\r
  moveq   R0,#1\r
  movne   R0,#0\r
  bx      LR\r
\r
ASM_PFX(ArmEnableVFP):\r
  # Read CPACR (Coprocessor Access Control Register)\r
  mrc     p15, 0, r0, c1, c0, 2\r
  # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
  orr     r0, r0, #0x00f00000\r
  # Write back CPACR (Coprocessor Access Control Register)\r
  mcr     p15, 0, r0, c1, c0, 2\r
  # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
  mov     r0, #0x40000000\r
  #TODO: Fixme - need compilation flag\r
  #fmxr    FPEXC, r0\r
  bx      lr\r
\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
Commit	Line	Data
3402aac7	1	#------------------------------------------------------------------------------\r
1e57a462	2	#\r
	3	# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
	4	# Copyright (c) 2011, ARM Limited. All rights reserved.\r
	5	#\r
	6	# This program and the accompanying materials\r
	7	# are licensed and made available under the terms and conditions of the BSD License\r
	8	# which accompanies this distribution. The full text of the license may be found at\r
	9	# http://opensource.org/licenses/bsd-license.php\r
	10	#\r
	11	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	#\r
	14	#------------------------------------------------------------------------------\r
	15	\r
	16	#include <AsmMacroIoLib.h>\r
	17	\r
	18	.text\r
	19	.align 2\r
	20	GCC_ASM_EXPORT(ArmDisableCachesAndMmu)\r
	21	GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)\r
	22	GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r
	23	GCC_ASM_EXPORT(ArmCleanDataCache)\r
	24	GCC_ASM_EXPORT(ArmInvalidateDataCache)\r
	25	GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r
	26	GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r
	27	GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r
	28	GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r
	29	GCC_ASM_EXPORT(ArmEnableMmu)\r
	30	GCC_ASM_EXPORT(ArmDisableMmu)\r
	31	GCC_ASM_EXPORT(ArmMmuEnabled)\r
	32	GCC_ASM_EXPORT(ArmEnableDataCache)\r
	33	GCC_ASM_EXPORT(ArmDisableDataCache)\r
	34	GCC_ASM_EXPORT(ArmEnableInstructionCache)\r
	35	GCC_ASM_EXPORT(ArmDisableInstructionCache)\r
	36	GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r
	37	GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r
	38	GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r
	39	GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r
	40	GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r
	41	GCC_ASM_EXPORT(ArmSetLowVectors)\r
	42	GCC_ASM_EXPORT(ArmSetHighVectors)\r
	43	GCC_ASM_EXPORT(ArmIsMpCore)\r
	44	GCC_ASM_EXPORT(ArmCallWFI)\r
	45	GCC_ASM_EXPORT(ArmReadMpidr)\r
	46	GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
	47	GCC_ASM_EXPORT(ArmEnableFiq)\r
	48	GCC_ASM_EXPORT(ArmDisableFiq)\r
	49	GCC_ASM_EXPORT(ArmEnableInterrupts)\r
	50	GCC_ASM_EXPORT(ArmDisableInterrupts)\r
	51	GCC_ASM_EXPORT (ArmEnableVFP)\r
	52	\r
	53	Arm11PartNumberMask: .word 0xFFF0\r
	54	Arm11PartNumber: .word 0xB020\r
	55	\r
	56	.set DC_ON, (0x1<<2)\r
	57	.set IC_ON, (0x1<<12)\r
	58	.set XP_ON, (0x1<<23)\r
	59	.set CTRL_M_BIT, (1 << 0)\r
	60	.set CTRL_C_BIT, (1 << 2)\r
	61	.set CTRL_I_BIT, (1 << 12)\r
	62	\r
	63	ASM_PFX(ArmDisableCachesAndMmu):\r
	64	mrc p15, 0, r0, c1, c0, 0 @ Get control register\r
	65	bic r0, r0, #CTRL_M_BIT @ Disable MMU\r
66	bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r
67	bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r
68	mcr p15, 0, r0, c1, c0, 0 @ Write control register\r
69	bx LR\r
70	\r
71	ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
72	mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB\r
73	bx lr\r
74	\r
75	ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
3402aac7	76	mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r
1e57a462	77	bx lr\r
	78	\r
	79	\r
	80	ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
3402aac7	81	mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r
1e57a462	82	bx lr\r
	83	\r
	84	\r
	85	ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
	86	mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r
	87	bx lr\r
	88	\r
	89	\r
	90	ASM_PFX(ArmCleanDataCache):\r
	91	mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache\r
	92	bx lr\r
	93	\r
	94	\r
	95	ASM_PFX(ArmCleanInvalidateDataCache):\r
	96	mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache\r
	97	bx lr\r
	98	\r
	99	\r
	100	ASM_PFX(ArmInvalidateDataCache):\r
	101	mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache\r
	102	bx lr\r
	103	\r
	104	\r
	105	ASM_PFX(ArmInvalidateInstructionCache):\r
	106	mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache\r
	107	mov R0,#0\r
	108	mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r
	109	bx lr\r
	110	\r
	111	ASM_PFX(ArmEnableMmu):\r
	112	mrc p15,0,R0,c1,c0,0\r
	113	orr R0,R0,#1\r
	114	mcr p15,0,R0,c1,c0,0\r
	115	bx LR\r
	116	\r
	117	ASM_PFX(ArmMmuEnabled):\r
	118	mrc p15,0,R0,c1,c0,0\r
	119	and R0,R0,#1\r
	120	bx LR\r
	121	\r
	122	ASM_PFX(ArmDisableMmu):\r
	123	mrc p15,0,R0,c1,c0,0\r
	124	bic R0,R0,#1\r
	125	mcr p15,0,R0,c1,c0,0\r
	126	mov R0,#0\r
	127	mcr p15,0,R0,c7,c10,4 @Data synchronization barrier\r
	128	mov R0,#0\r
	129	mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r
	130	bx LR\r
	131	\r
	132	ASM_PFX(ArmEnableDataCache):\r
	133	LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r
	134	mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
	135	orr R0,R0,R1 @Set C bit\r
	136	mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
	137	bx LR\r
3402aac7	138	\r
1e57a462	139	ASM_PFX(ArmDisableDataCache):\r
	140	LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r
	141	mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
	142	bic R0,R0,R1 @Clear C bit\r
	143	mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
	144	bx LR\r
	145	\r
	146	ASM_PFX(ArmEnableInstructionCache):\r
	147	ldr R1,=IC_ON\r
	148	mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
	149	orr R0,R0,R1 @Set I bit\r
	150	mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
	151	bx LR\r
3402aac7	152	\r
1e57a462	153	ASM_PFX(ArmDisableInstructionCache):\r
	154	ldr R1,=IC_ON\r
	155	mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
	156	bic R0,R0,R1 @Clear I bit.\r
	157	mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
	158	bx LR\r
	159	\r
	160	ASM_PFX(ArmEnableBranchPrediction):\r
	161	mrc p15, 0, r0, c1, c0, 0\r
	162	orr r0, r0, #0x00000800\r
	163	mcr p15, 0, r0, c1, c0, 0\r
	164	bx LR\r
	165	\r
	166	ASM_PFX(ArmDisableBranchPrediction):\r
	167	mrc p15, 0, r0, c1, c0, 0\r
	168	bic r0, r0, #0x00000800\r
	169	mcr p15, 0, r0, c1, c0, 0\r
	170	bx LR\r
	171	\r
	172	ASM_PFX(ArmDataMemoryBarrier):\r
	173	mov R0, #0\r
3402aac7	174	mcr P15, #0, R0, C7, C10, #5\r
1e57a462	175	bx LR\r
3402aac7	176	\r
1e57a462	177	ASM_PFX(ArmDataSyncronizationBarrier):\r
1e57a462	178	mov R0, #0\r
3402aac7	179	mcr P15, #0, R0, C7, C10, #4\r
1e57a462	180	bx LR\r
3402aac7	181	\r
1e57a462	182	ASM_PFX(ArmInstructionSynchronizationBarrier):\r
1e57a462	183	mov R0, #0\r
3402aac7	184	mcr P15, #0, R0, C7, C5, #4\r
1e57a462	185	bx LR\r
	186	\r
	187	ASM_PFX(ArmSetLowVectors):\r
	188	mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
	189	bic r0, r0, #0x00002000 @ clear V bit\r
	190	mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
	191	bx LR\r
	192	\r
	193	ASM_PFX(ArmSetHighVectors):\r
	194	mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
	195	orr r0, r0, #0x00002000 @ clear V bit\r
	196	mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
	197	bx LR\r
	198	\r
	199	ASM_PFX(ArmIsMpCore):\r
	200	push { r1 }\r
	201	mrc p15, 0, r0, c0, c0, 0\r
	202	# Extract Part Number to check it is an ARM11MP core (0xB02)\r
	203	LoadConstantToReg (Arm11PartNumberMask, r1)\r
	204	and r0, r0, r1\r
	205	LoadConstantToReg (Arm11PartNumber, r1)\r
	206	cmp r0, r1\r
	207	movne r0, #0\r
	208	pop { r1 }\r
3402aac7	209	bx lr\r
1e57a462	210	\r
	211	ASM_PFX(ArmCallWFI):\r
	212	wfi\r
	213	bx lr\r
	214	\r
	215	ASM_PFX(ArmReadMpidr):\r
	216	mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
	217	bx lr\r
	218	\r
	219	ASM_PFX(ArmEnableFiq):\r
	220	mrs R0,CPSR\r
	221	bic R0,R0,#0x40 @Enable FIQ interrupts\r
	222	msr CPSR_c,R0\r
	223	bx LR\r
	224	\r
	225	ASM_PFX(ArmDisableFiq):\r
	226	mrs R0,CPSR\r
	227	orr R1,R0,#0x40 @Disable FIQ interrupts\r
	228	msr CPSR_c,R1\r
	229	tst R0,#0x80\r
	230	moveq R0,#1\r
	231	movne R0,#0\r
	232	bx LR\r
	233	\r
	234	ASM_PFX(ArmEnableInterrupts):\r
	235	mrs R0,CPSR\r
	236	bic R0,R0,#0x80 @Enable IRQ interrupts\r
	237	msr CPSR_c,R0\r
	238	bx LR\r
	239	\r
	240	ASM_PFX(ArmDisableInterrupts):\r
	241	mrs R0,CPSR\r
	242	orr R1,R0,#0x80 @Disable IRQ interrupts\r
	243	msr CPSR_c,R1\r
	244	tst R0,#0x80\r
	245	moveq R0,#1\r
	246	movne R0,#0\r
	247	bx LR\r
	248	\r
	249	ASM_PFX(ArmEnableVFP):\r
	250	# Read CPACR (Coprocessor Access Control Register)\r
	251	mrc p15, 0, r0, c1, c0, 2\r
	252	# Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
	253	orr r0, r0, #0x00f00000\r
	254	# Write back CPACR (Coprocessor Access Control Register)\r
	255	mcr p15, 0, r0, c1, c0, 2\r
	256	# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
	257	mov r0, #0x40000000\r
	258	#TODO: Fixme - need compilation flag\r
	259	#fmxr FPEXC, r0\r
	260	bx lr\r
	261	\r
	262	ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r