]>
Commit | Line | Data |
---|---|---|
2ef2b01e A |
1 | #------------------------------------------------------------------------------ |
2 | # | |
d6ebcab7 | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
2ef2b01e | 4 | # |
d6ebcab7 | 5 | # This program and the accompanying materials |
2ef2b01e A |
6 | # are licensed and made available under the terms and conditions of the BSD License |
7 | # which accompanies this distribution. The full text of the license may be found at | |
8 | # http://opensource.org/licenses/bsd-license.php | |
9 | # | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | # | |
13 | #------------------------------------------------------------------------------ | |
14 | ||
15 | .text | |
16 | .align 2 | |
17 | .globl ASM_PFX(ArmCleanInvalidateDataCache) | |
63ca7402 | 18 | INTERWORK_FUNC(ArmCleanInvalidateDataCache) |
2ef2b01e | 19 | .globl ASM_PFX(ArmCleanDataCache) |
63ca7402 | 20 | INTERWORK_FUNC(ArmCleanDataCache) |
2ef2b01e | 21 | .globl ASM_PFX(ArmInvalidateDataCache) |
63ca7402 | 22 | INTERWORK_FUNC(ArmInvalidateDataCache) |
2ef2b01e | 23 | .globl ASM_PFX(ArmInvalidateInstructionCache) |
63ca7402 | 24 | INTERWORK_FUNC(ArmInvalidateInstructionCache) |
2ef2b01e | 25 | .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA) |
63ca7402 | 26 | INTERWORK_FUNC(ArmInvalidateDataCacheEntryByMVA) |
2ef2b01e | 27 | .globl ASM_PFX(ArmCleanDataCacheEntryByMVA) |
63ca7402 | 28 | INTERWORK_FUNC(ArmCleanDataCacheEntryByMVA) |
2ef2b01e | 29 | .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA) |
63ca7402 | 30 | INTERWORK_FUNC(ArmCleanInvalidateDataCacheEntryByMVA) |
2ef2b01e | 31 | .globl ASM_PFX(ArmEnableMmu) |
63ca7402 | 32 | INTERWORK_FUNC(ArmEnableMmu) |
2ef2b01e | 33 | .globl ASM_PFX(ArmDisableMmu) |
63ca7402 | 34 | INTERWORK_FUNC(ArmDisableMmu) |
c2b5ca8b | 35 | .globl ASM_PFX(ArmMmuEnabled) |
63ca7402 | 36 | INTERWORK_FUNC(ArmMmuEnabled) |
2ef2b01e | 37 | .globl ASM_PFX(ArmEnableDataCache) |
63ca7402 | 38 | INTERWORK_FUNC(ArmEnableDataCache) |
2ef2b01e | 39 | .globl ASM_PFX(ArmDisableDataCache) |
63ca7402 | 40 | INTERWORK_FUNC(ArmDisableDataCache) |
2ef2b01e | 41 | .globl ASM_PFX(ArmEnableInstructionCache) |
63ca7402 | 42 | INTERWORK_FUNC(ArmEnableInstructionCache) |
2ef2b01e | 43 | .globl ASM_PFX(ArmDisableInstructionCache) |
63ca7402 | 44 | INTERWORK_FUNC(ArmDisableInstructionCache) |
2ef2b01e | 45 | .globl ASM_PFX(ArmEnableBranchPrediction) |
63ca7402 | 46 | INTERWORK_FUNC(ArmEnableBranchPrediction) |
2ef2b01e | 47 | .globl ASM_PFX(ArmDisableBranchPrediction) |
63ca7402 | 48 | INTERWORK_FUNC(ArmDisableBranchPrediction) |
026c3d34 | 49 | .globl ASM_PFX(ArmDataMemoryBarrier) |
63ca7402 | 50 | INTERWORK_FUNC(ArmDataMemoryBarrier) |
026c3d34 | 51 | .globl ASM_PFX(ArmDataSyncronizationBarrier) |
63ca7402 | 52 | INTERWORK_FUNC(ArmDataSyncronizationBarrier) |
026c3d34 | 53 | .globl ASM_PFX(ArmInstructionSynchronizationBarrier) |
63ca7402 | 54 | INTERWORK_FUNC(ArmInstructionSynchronizationBarrier) |
026c3d34 | 55 | |
2ef2b01e A |
56 | |
57 | .set DC_ON, (0x1<<2) | |
58 | .set IC_ON, (0x1<<12) | |
59 | .set XP_ON, (0x1<<23) | |
60 | ||
61 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA): | |
62 | mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line | |
63 | bx lr | |
64 | ||
65 | ||
66 | ASM_PFX(ArmCleanDataCacheEntryByMVA): | |
67 | mcr p15, 0, r0, c7, c10, 1 @clean single data cache line | |
68 | bx lr | |
69 | ||
70 | ||
71 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): | |
72 | mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line | |
73 | bx lr | |
74 | ||
75 | ||
76 | ASM_PFX(ArmCleanDataCache): | |
77 | mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache | |
78 | bx lr | |
79 | ||
80 | ||
81 | ASM_PFX(ArmCleanInvalidateDataCache): | |
82 | mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache | |
83 | bx lr | |
84 | ||
85 | ||
86 | ASM_PFX(ArmInvalidateDataCache): | |
87 | mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache | |
88 | bx lr | |
89 | ||
90 | ||
91 | ASM_PFX(ArmInvalidateInstructionCache): | |
92 | mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache | |
93 | mov R0,#0 | |
94 | mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer | |
95 | bx lr | |
96 | ||
97 | ASM_PFX(ArmEnableMmu): | |
98 | mrc p15,0,R0,c1,c0,0 | |
99 | orr R0,R0,#1 | |
100 | mcr p15,0,R0,c1,c0,0 | |
101 | bx LR | |
102 | ||
c2b5ca8b A |
103 | ASM_PFX(ArmMmuEnabled): |
104 | mrc p15,0,R0,c1,c0,0 | |
105 | and R0,R0,#1 | |
106 | bx LR | |
107 | ||
2ef2b01e A |
108 | ASM_PFX(ArmDisableMmu): |
109 | mrc p15,0,R0,c1,c0,0 | |
110 | bic R0,R0,#1 | |
111 | mcr p15,0,R0,c1,c0,0 | |
112 | mov R0,#0 | |
113 | mcr p15,0,R0,c7,c10,4 @Data synchronization barrier | |
114 | mov R0,#0 | |
115 | mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer | |
116 | bx LR | |
117 | ||
118 | ASM_PFX(ArmEnableDataCache): | |
119 | ldr R1,=DC_ON | |
120 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
121 | orr R0,R0,R1 @Set C bit | |
122 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
123 | bx LR | |
124 | ||
125 | ASM_PFX(ArmDisableDataCache): | |
126 | ldr R1,=DC_ON | |
127 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
128 | bic R0,R0,R1 @Clear C bit | |
129 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
130 | bx LR | |
131 | ||
132 | ASM_PFX(ArmEnableInstructionCache): | |
133 | ldr R1,=IC_ON | |
134 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
135 | orr R0,R0,R1 @Set I bit | |
136 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
137 | bx LR | |
138 | ||
139 | ASM_PFX(ArmDisableInstructionCache): | |
140 | ldr R1,=IC_ON | |
141 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data | |
142 | bic R0,R0,R1 @Clear I bit. | |
143 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data | |
144 | bx LR | |
145 | ||
146 | ASM_PFX(ArmEnableBranchPrediction): | |
147 | mrc p15, 0, r0, c1, c0, 0 | |
148 | orr r0, r0, #0x00000800 | |
149 | mcr p15, 0, r0, c1, c0, 0 | |
150 | bx LR | |
151 | ||
152 | ASM_PFX(ArmDisableBranchPrediction): | |
153 | mrc p15, 0, r0, c1, c0, 0 | |
154 | bic r0, r0, #0x00000800 | |
155 | mcr p15, 0, r0, c1, c0, 0 | |
156 | bx LR | |
157 | ||
026c3d34 | 158 | ASM_PFX(ArmDataMemoryBarrier): |
159 | mov R0, #0 | |
160 | mcr P15, #0, R0, C7, C10, #5 | |
161 | bx LR | |
162 | ||
163 | ASM_PFX(ArmDataSyncronizationBarrier): | |
164 | mov R0, #0 | |
165 | mcr P15, #0, R0, C7, C10, #4 | |
166 | bx LR | |
167 | ||
168 | ASM_PFX(ArmInstructionSynchronizationBarrier): | |
169 | mov R0, #0 | |
170 | mcr P15, #0, R0, C7, C5, #4 | |
171 | bx LR | |
172 | ||
173 | ||
2ef2b01e | 174 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED |