[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm11 / Arm11Support.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmCleanInvalidateDataCache
    EXPORT  ArmCleanDataCache
    EXPORT  ArmInvalidateDataCache
    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmMmuEnabled
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction


DC_ON       EQU     ( 0x1:SHL:2 )
IC_ON       EQU     ( 0x1:SHL:12 )
XP_ON       EQU     ( 0x1:SHL:23 )


    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8


ArmInvalidateDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
  bx      lr


ArmCleanDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  bx      lr


ArmCleanInvalidateDataCacheEntryByMVA
  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  bx      lr


ArmCleanDataCache
  mcr     p15, 0, r0, c7, c10, 0  ; clean entire data cache
  bx      lr


ArmCleanInvalidateDataCache
  mcr     p15, 0, r0, c7, c14, 0  ; clean and invalidate entire data cache
  bx      lr


ArmInvalidateDataCache
  mcr     p15, 0, r0, c7, c6, 0  ; invalidate entire data cache
  bx      lr


ArmInvalidateInstructionCache
  mcr     p15, 0, r0, c7, c5, 0  ;invalidate entire instruction cache
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4       ;Flush Prefetch buffer
  bx      lr

ArmEnableMmu
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  bx      LR

ArmMmuEnabled
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  bx      LR

ArmDisableMmu
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  mov     R0,#0
  mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4      ;Flush Prefetch buffer
  bx      LR

ArmEnableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR
    
ArmDisableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  BIC     R0,R0,R1              ;Clear C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR

ArmEnableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  ORR     R0,R0,R1             ;Set I bit
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR
  
ArmDisableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  BIC     R0,R0,R1             ;Clear I bit.
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR

ArmEnableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

ArmDisableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

    END
Commit	Line	Data
2ef2b01e A	1	//------------------------------------------------------------------------------
	2	//
	3	// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	//
	5	// All rights reserved. This program and the accompanying materials
	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmCleanInvalidateDataCache
	16	EXPORT ArmCleanDataCache
	17	EXPORT ArmInvalidateDataCache
	18	EXPORT ArmInvalidateInstructionCache
	19	EXPORT ArmInvalidateDataCacheEntryByMVA
	20	EXPORT ArmCleanDataCacheEntryByMVA
	21	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	22	EXPORT ArmEnableMmu
	23	EXPORT ArmDisableMmu
c2b5ca8b	24	EXPORT ArmMmuEnabled
2ef2b01e A	25	EXPORT ArmEnableDataCache
	26	EXPORT ArmDisableDataCache
	27	EXPORT ArmEnableInstructionCache
	28	EXPORT ArmDisableInstructionCache
	29	EXPORT ArmEnableBranchPrediction
	30	EXPORT ArmDisableBranchPrediction
	31
	32
	33	DC_ON EQU ( 0x1:SHL:2 )
	34	IC_ON EQU ( 0x1:SHL:12 )
	35	XP_ON EQU ( 0x1:SHL:23 )
	36
	37
	38	AREA ArmCacheLib, CODE, READONLY
	39	PRESERVE8
	40
	41
	42	ArmInvalidateDataCacheEntryByMVA
	43	mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
	44	bx lr
	45
	46
	47	ArmCleanDataCacheEntryByMVA
	48	mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
	49	bx lr
	50
	51
	52	ArmCleanInvalidateDataCacheEntryByMVA
	53	mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
	54	bx lr
	55
	56
	57	ArmCleanDataCache
	58	mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
	59	bx lr
	60
	61
	62	ArmCleanInvalidateDataCache
	63	mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
	64	bx lr
	65
	66
	67	ArmInvalidateDataCache
	68	mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
	69	bx lr
	70
	71
	72	ArmInvalidateInstructionCache
	73	mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
	74	mov R0,#0
	75	mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
	76	bx lr
	77
	78	ArmEnableMmu
	79	mrc p15,0,R0,c1,c0,0
	80	orr R0,R0,#1
	81	mcr p15,0,R0,c1,c0,0
	82	bx LR
	83
c2b5ca8b A	84	ArmMmuEnabled
	85	mrc p15,0,R0,c1,c0,0
	86	and R0,R0,#1
	87	bx LR
	88
2ef2b01e A	89	ArmDisableMmu
	90	mrc p15,0,R0,c1,c0,0
	91	bic R0,R0,#1
	92	mcr p15,0,R0,c1,c0,0
	93	mov R0,#0
	94	mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
	95	mov R0,#0
	96	mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
	97	bx LR
	98
	99	ArmEnableDataCache
	100	LDR R1,=DC_ON
	101	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	102	ORR R0,R0,R1 ;Set C bit
	103	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	104	BX LR
	105
	106	ArmDisableDataCache
	107	LDR R1,=DC_ON
	108	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	109	BIC R0,R0,R1 ;Clear C bit
	110	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	111	BX LR
	112
	113	ArmEnableInstructionCache
	114	LDR R1,=IC_ON
	115	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	116	ORR R0,R0,R1 ;Set I bit
	117	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	118	BX LR
	119
	120	ArmDisableInstructionCache
	121	LDR R1,=IC_ON
	122	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	123	BIC R0,R0,R1 ;Clear I bit.
	124	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	125	BX LR
	126
	127	ArmEnableBranchPrediction
	128	mrc p15, 0, r0, c1, c0, 0
	129	orr r0, r0, #0x00000800
	130	mcr p15, 0, r0, c1, c0, 0
	131	bx LR
	132
	133	ArmDisableBranchPrediction
	134	mrc p15, 0, r0, c1, c0, 0
	135	bic r0, r0, #0x00000800
	136	mcr p15, 0, r0, c1, c0, 0
	137	bx LR
	138
	139	END