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2ef2b01e A |
1 | /** @file |
2 | ||
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
2ef2b01e | 4 | |
d6ebcab7 | 5 | This program and the accompanying materials |
2ef2b01e A |
6 | are licensed and made available under the terms and conditions of the BSD License |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #include <Chipset/ARM926EJ-S.h> | |
16 | #include <Library/ArmLib.h> | |
17 | #include <Library/BaseMemoryLib.h> | |
18 | #include <Library/MemoryAllocationLib.h> | |
1bfda055 | 19 | #include <Library/DebugLib.h> |
2ef2b01e A |
20 | |
21 | VOID | |
22 | FillTranslationTable ( | |
23 | IN UINT32 *TranslationTable, | |
24 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion | |
25 | ) | |
26 | { | |
27 | UINT32 *Entry; | |
28 | UINTN Sections; | |
29 | UINTN Index; | |
30 | UINT32 Attributes; | |
31 | UINT32 PhysicalBase = MemoryRegion->PhysicalBase; | |
32 | ||
33 | switch (MemoryRegion->Attributes) { | |
34 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: | |
35 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK; | |
36 | break; | |
37 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: | |
38 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH; | |
39 | break; | |
40 | case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: | |
1bfda055 | 41 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED; |
42 | break; | |
43 | case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK: | |
44 | case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH: | |
45 | case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED: | |
46 | ASSERT(0); // Trustzone is not supported on ARMv5 | |
2ef2b01e A |
47 | default: |
48 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED; | |
49 | break; | |
50 | } | |
51 | ||
52 | Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); | |
53 | Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE; | |
54 | ||
55 | for (Index = 0; Index < Sections; Index++) | |
56 | { | |
57 | *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes; | |
58 | PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; | |
59 | } | |
60 | } | |
61 | ||
62 | VOID | |
63 | EFIAPI | |
64 | ArmConfigureMmu ( | |
65 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, | |
66 | OUT VOID **TranslationTableBase OPTIONAL, | |
67 | OUT UINTN *TranslationTableSize OPTIONAL | |
68 | ) | |
69 | { | |
70 | VOID *TranslationTable; | |
71 | ||
72 | // Allocate pages for translation table. | |
73 | TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT)); | |
74 | TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK); | |
75 | ||
76 | if (TranslationTableBase != NULL) { | |
77 | *TranslationTableBase = TranslationTable; | |
78 | } | |
79 | ||
80 | if (TranslationTableBase != NULL) { | |
81 | *TranslationTableSize = TRANSLATION_TABLE_SIZE; | |
82 | } | |
83 | ||
84 | ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE); | |
85 | ||
86 | ArmCleanInvalidateDataCache(); | |
87 | ArmInvalidateInstructionCache(); | |
88 | ArmInvalidateTlb(); | |
89 | ||
90 | ArmDisableDataCache(); | |
91 | ArmDisableInstructionCache(); | |
92 | ArmDisableMmu(); | |
93 | ||
94 | // Make sure nothing sneaked into the cache | |
95 | ArmCleanInvalidateDataCache(); | |
96 | ArmInvalidateInstructionCache(); | |
97 | ||
98 | while (MemoryTable->Length != 0) { | |
99 | FillTranslationTable(TranslationTable, MemoryTable); | |
100 | MemoryTable++; | |
101 | } | |
102 | ||
1bfda055 | 103 | ArmSetTTBR0(TranslationTable); |
2ef2b01e A |
104 | |
105 | ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) | | |
106 | DOMAIN_ACCESS_CONTROL_NONE(14) | | |
107 | DOMAIN_ACCESS_CONTROL_NONE(13) | | |
108 | DOMAIN_ACCESS_CONTROL_NONE(12) | | |
109 | DOMAIN_ACCESS_CONTROL_NONE(11) | | |
110 | DOMAIN_ACCESS_CONTROL_NONE(10) | | |
111 | DOMAIN_ACCESS_CONTROL_NONE( 9) | | |
112 | DOMAIN_ACCESS_CONTROL_NONE( 8) | | |
113 | DOMAIN_ACCESS_CONTROL_NONE( 7) | | |
114 | DOMAIN_ACCESS_CONTROL_NONE( 6) | | |
115 | DOMAIN_ACCESS_CONTROL_NONE( 5) | | |
116 | DOMAIN_ACCESS_CONTROL_NONE( 4) | | |
117 | DOMAIN_ACCESS_CONTROL_NONE( 3) | | |
118 | DOMAIN_ACCESS_CONTROL_NONE( 2) | | |
119 | DOMAIN_ACCESS_CONTROL_NONE( 1) | | |
120 | DOMAIN_ACCESS_CONTROL_MANAGER(0)); | |
121 | ||
122 | ArmEnableInstructionCache(); | |
123 | ArmEnableDataCache(); | |
124 | ArmEnableMmu(); | |
125 | } | |
026c3d34 | 126 | |
127 | ||
026c3d34 | 128 |