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1e57a462 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
6f050ad6 | 4 | Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r |
1e57a462 | 5 | \r |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <Chipset/ARM926EJ-S.h>\r | |
17 | #include <Library/ArmLib.h>\r | |
18 | #include <Library/BaseMemoryLib.h>\r | |
19 | #include <Library/MemoryAllocationLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | \r | |
22 | VOID\r | |
23 | FillTranslationTable (\r | |
24 | IN UINT32 *TranslationTable,\r | |
25 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r | |
26 | )\r | |
27 | {\r | |
28 | UINT32 *Entry;\r | |
29 | UINTN Sections;\r | |
30 | UINTN Index;\r | |
31 | UINT32 Attributes;\r | |
32 | UINT32 PhysicalBase = MemoryRegion->PhysicalBase;\r | |
33 | \r | |
34 | switch (MemoryRegion->Attributes) {\r | |
35 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r | |
36 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;\r | |
37 | break;\r | |
38 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r | |
39 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;\r | |
40 | break;\r | |
41 | case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r | |
42 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;\r | |
43 | break;\r | |
44 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r | |
45 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r | |
46 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r | |
47 | ASSERT(0); // Trustzone is not supported on ARMv5\r | |
48 | default:\r | |
49 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;\r | |
50 | break;\r | |
51 | }\r | |
52 | \r | |
53 | Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r | |
54 | Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;\r | |
55 | \r | |
56 | // The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary\r | |
57 | ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);\r | |
58 | \r | |
59 | for (Index = 0; Index < Sections; Index++)\r | |
60 | {\r | |
61 | *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r | |
62 | PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r | |
63 | }\r | |
64 | }\r | |
65 | \r | |
6f050ad6 | 66 | RETURN_STATUS\r |
1e57a462 | 67 | EFIAPI\r |
68 | ArmConfigureMmu (\r | |
69 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r | |
6f050ad6 OM |
70 | OUT VOID **TranslationTableBase OPTIONAL,\r |
71 | OUT UINTN *TranslationTableSize OPTIONAL\r | |
1e57a462 | 72 | )\r |
73 | {\r | |
74 | VOID *TranslationTable;\r | |
75 | \r | |
76 | // Allocate pages for translation table.\r | |
6f050ad6 OM |
77 | TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));\r |
78 | if (TranslationTable == NULL) {\r | |
79 | return RETURN_OUT_OF_RESOURCES;\r | |
80 | }\r | |
1e57a462 | 81 | TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);\r |
82 | \r | |
83 | if (TranslationTableBase != NULL) {\r | |
84 | *TranslationTableBase = TranslationTable;\r | |
85 | }\r | |
86 | \r | |
87 | if (TranslationTableBase != NULL) {\r | |
88 | *TranslationTableSize = TRANSLATION_TABLE_SIZE;\r | |
89 | }\r | |
90 | \r | |
91 | ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);\r | |
92 | \r | |
93 | ArmCleanInvalidateDataCache();\r | |
94 | ArmInvalidateInstructionCache();\r | |
95 | ArmInvalidateTlb();\r | |
96 | \r | |
97 | ArmDisableDataCache();\r | |
98 | ArmDisableInstructionCache();\r | |
99 | ArmDisableMmu();\r | |
100 | \r | |
101 | // Make sure nothing sneaked into the cache\r | |
102 | ArmCleanInvalidateDataCache();\r | |
103 | ArmInvalidateInstructionCache();\r | |
104 | \r | |
105 | while (MemoryTable->Length != 0) {\r | |
106 | FillTranslationTable(TranslationTable, MemoryTable);\r | |
107 | MemoryTable++;\r | |
108 | }\r | |
109 | \r | |
110 | ArmSetTTBR0(TranslationTable);\r | |
111 | \r | |
112 | ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |\r | |
113 | DOMAIN_ACCESS_CONTROL_NONE(14) |\r | |
114 | DOMAIN_ACCESS_CONTROL_NONE(13) |\r | |
115 | DOMAIN_ACCESS_CONTROL_NONE(12) |\r | |
116 | DOMAIN_ACCESS_CONTROL_NONE(11) |\r | |
117 | DOMAIN_ACCESS_CONTROL_NONE(10) |\r | |
118 | DOMAIN_ACCESS_CONTROL_NONE( 9) |\r | |
119 | DOMAIN_ACCESS_CONTROL_NONE( 8) |\r | |
120 | DOMAIN_ACCESS_CONTROL_NONE( 7) |\r | |
121 | DOMAIN_ACCESS_CONTROL_NONE( 6) |\r | |
122 | DOMAIN_ACCESS_CONTROL_NONE( 5) |\r | |
123 | DOMAIN_ACCESS_CONTROL_NONE( 4) |\r | |
124 | DOMAIN_ACCESS_CONTROL_NONE( 3) |\r | |
125 | DOMAIN_ACCESS_CONTROL_NONE( 2) |\r | |
126 | DOMAIN_ACCESS_CONTROL_NONE( 1) |\r | |
127 | DOMAIN_ACCESS_CONTROL_MANAGER(0));\r | |
128 | \r | |
129 | ArmEnableInstructionCache();\r | |
130 | ArmEnableDataCache();\r | |
131 | ArmEnableMmu();\r | |
1e57a462 | 132 | \r |
6f050ad6 OM |
133 | return RETURN_SUCCESS;\r |
134 | }\r |