| 1e57a462 |
1 | #------------------------------------------------------------------------------ \r |
| 2 | #\r |
| 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | #\r |
| 5 | # This program and the accompanying materials\r |
| 6 | # are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | # which accompanies this distribution. The full text of the license may be found at\r |
| 8 | # http://opensource.org/licenses/bsd-license.php\r |
| 9 | #\r |
| 10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | #\r |
| 13 | #------------------------------------------------------------------------------\r |
| 14 | \r |
| 15 | .text\r |
| 16 | .align 2\r |
| 17 | GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r |
| 18 | GCC_ASM_EXPORT(ArmCleanDataCache)\r |
| 19 | GCC_ASM_EXPORT(ArmInvalidateDataCache)\r |
| 20 | GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r |
| 21 | GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r |
| 22 | GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r |
| 23 | GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r |
| 24 | GCC_ASM_EXPORT(ArmEnableMmu)\r |
| 25 | GCC_ASM_EXPORT(ArmDisableMmu)\r |
| 26 | GCC_ASM_EXPORT(ArmMmuEnabled)\r |
| 27 | GCC_ASM_EXPORT(ArmEnableDataCache)\r |
| 28 | GCC_ASM_EXPORT(ArmDisableDataCache)\r |
| 29 | GCC_ASM_EXPORT(ArmEnableInstructionCache)\r |
| 30 | GCC_ASM_EXPORT(ArmDisableInstructionCache)\r |
| 31 | GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r |
| 32 | GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r |
| 33 | GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r |
| 34 | GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r |
| 35 | GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r |
| 36 | \r |
| 37 | \r |
| 38 | .set DC_ON, (1<<2)\r |
| 39 | .set IC_ON, (1<<12)\r |
| 40 | \r |
| 41 | #------------------------------------------------------------------------------\r |
| 42 | \r |
| 43 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r |
| 44 | mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line \r |
| 45 | bx lr\r |
| 46 | \r |
| 47 | ASM_PFX(ArmCleanDataCacheEntryByMVA):\r |
| 48 | mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line \r |
| 49 | bx lr\r |
| 50 | \r |
| 51 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r |
| 52 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line\r |
| 53 | bx lr\r |
| 54 | \r |
| 55 | ASM_PFX(ArmEnableInstructionCache):\r |
| 56 | ldr r1,=IC_ON\r |
| 57 | mrc p15,0,r0,c1,c0,0 @Read control register configuration data\r |
| 58 | orr r0,r0,r1 @Set I bit\r |
| 59 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 60 | bx LR\r |
| 61 | \r |
| 62 | ASM_PFX(ArmDisableInstructionCache):\r |
| 63 | ldr r1,=IC_ON\r |
| 64 | mrc p15,0,r0,c1,c0,0 @Read control register configuration data\r |
| 65 | bic r0,r0,r1 @Clear I bit.\r |
| 66 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 67 | bx LR\r |
| 68 | \r |
| 69 | ASM_PFX(ArmInvalidateInstructionCache):\r |
| 70 | mov r0,#0\r |
| 71 | mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache. \r |
| 72 | @Also flushes the branch target cache.\r |
| 73 | mov r0,#0\r |
| 74 | mcr p15,0,r0,c7,c10,4 @Data write buffer\r |
| 75 | bx LR\r |
| 76 | \r |
| 77 | ASM_PFX(ArmEnableMmu):\r |
| 78 | mrc p15,0,R0,c1,c0,0\r |
| 79 | orr R0,R0,#1\r |
| 80 | mcr p15,0,R0,c1,c0,0\r |
| 81 | bx LR\r |
| 82 | \r |
| 83 | ASM_PFX(ArmMmuEnabled):\r |
| 84 | mrc p15,0,R0,c1,c0,0\r |
| 85 | and R0,R0,#1\r |
| 86 | bx LR\r |
| 87 | \r |
| 88 | ASM_PFX(ArmDisableMmu):\r |
| 89 | mrc p15,0,R0,c1,c0,0\r |
| 90 | bic R0,R0,#1\r |
| 91 | mcr p15,0,R0,c1,c0,0\r |
| 92 | mov R0,#0\r |
| 93 | mcr p15,0,R0,c7,c10,4 @Drain write buffer\r |
| 94 | bx LR\r |
| 95 | \r |
| 96 | ASM_PFX(ArmEnableDataCache):\r |
| 97 | ldr R1,=DC_ON\r |
| 98 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r |
| 99 | orr R0,R0,R1 @Set C bit\r |
| 100 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 101 | bx LR\r |
| 102 | \r |
| 103 | ASM_PFX(ArmDisableDataCache):\r |
| 104 | ldr R1,=DC_ON\r |
| 105 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r |
| 106 | bic R0,R0,R1 @Clear C bit\r |
| 107 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r |
| 108 | bx LR\r |
| 109 | \r |
| 110 | ASM_PFX(ArmCleanDataCache):\r |
| 111 | mrc p15,0,r15,c7,c10,3\r |
| 112 | bne ASM_PFX(ArmCleanDataCache)\r |
| 113 | mov R0,#0\r |
| 114 | mcr p15,0,R0,c7,c10,4 @Drain write buffer\r |
| 115 | bx LR\r |
| 116 | \r |
| 117 | ASM_PFX(ArmInvalidateDataCache):\r |
| 118 | mov R0,#0\r |
| 119 | mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache\r |
| 120 | mov R0,#0\r |
| 121 | mcr p15,0,R0,c7,c10,4 @Drain write buffer\r |
| 122 | bx LR\r |
| 123 | \r |
| 124 | ASM_PFX(ArmCleanInvalidateDataCache):\r |
| 125 | mrc p15,0,r15,c7,c14,3\r |
| 126 | bne ASM_PFX(ArmCleanInvalidateDataCache)\r |
| 127 | mov R0,#0\r |
| 128 | mcr p15,0,R0,c7,c10,4 @Drain write buffer\r |
| 129 | bx LR\r |
| 130 | \r |
| 131 | ASM_PFX(ArmEnableBranchPrediction):\r |
| 132 | bx LR @Branch prediction is not supported.\r |
| 133 | \r |
| 134 | ASM_PFX(ArmDisableBranchPrediction):\r |
| 135 | bx LR @Branch prediction is not supported.\r |
| 136 | \r |
| 137 | ASM_PFX(ArmDataMemoryBarrier):\r |
| 138 | mov R0, #0\r |
| 139 | mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?\r |
| 140 | bx LR\r |
| 141 | \r |
| 142 | ASM_PFX(ArmDataSyncronizationBarrier):\r |
| 143 | mov R0, #0\r |
| 144 | mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?\r |
| 145 | bx LR\r |
| 146 | \r |
| 147 | ASM_PFX(ArmInstructionSynchronizationBarrier):\r |
| 148 | mov R0, #0\r |
| 149 | mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?\r |
| 150 | bx LR\r |
| 151 | \r |
| 152 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |
| 153 | \r |
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