[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm9 / Arm9Support.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmCleanInvalidateDataCache
    EXPORT  ArmCleanDataCache
    EXPORT  ArmInvalidateDataCache
    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmMmuEnabled
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction


DC_ON       EQU     ( 0x1:SHL:2 )
IC_ON       EQU     ( 0x1:SHL:12 )

    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8


ArmInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
  BX      lr


ArmCleanDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  BX      lr


ArmCleanInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  BX      lr

ArmEnableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  ORR     R0,R0,R1             ;Set I bit
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR
  
ArmDisableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  BIC     R0,R0,R1             ;Clear I bit.
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR

ArmInvalidateInstructionCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
  BX      LR

ArmEnableMmu
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  bx      LR

ArmMmuEnabled
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  bx      LR

ArmDisableMmu
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  mov     R0,#0
  mcr     p15,0,R0,c7,c10,4     ;Drain write buffer
  bx      LR

ArmEnableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR
    
ArmDisableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  BIC     R0,R0,R1              ;Clear C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR

ArmCleanDataCache
  MRC     p15,0,r15,c7,c10,3
  BNE     ArmCleanDataCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4	    ;Drain write buffer
  BX      LR

ArmInvalidateDataCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
  BX      LR
  
ArmCleanInvalidateDataCache
  MRC     p15,0,r15,c7,c14,3
  BNE     ArmCleanInvalidateDataCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4	    ;Drain write buffer
  BX      LR

ArmEnableBranchPrediction
  bx      LR                    ;Branch prediction is not supported.

ArmDisableBranchPrediction
  bx      LR                    ;Branch prediction is not supported.

    END
Commit	Line	Data
2ef2b01e A	1	//------------------------------------------------------------------------------
	2	//
	3	// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	//
	5	// All rights reserved. This program and the accompanying materials
	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmCleanInvalidateDataCache
	16	EXPORT ArmCleanDataCache
	17	EXPORT ArmInvalidateDataCache
	18	EXPORT ArmInvalidateInstructionCache
	19	EXPORT ArmInvalidateDataCacheEntryByMVA
	20	EXPORT ArmCleanDataCacheEntryByMVA
	21	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	22	EXPORT ArmEnableMmu
	23	EXPORT ArmDisableMmu
c2b5ca8b	24	EXPORT ArmMmuEnabled
2ef2b01e A	25	EXPORT ArmEnableDataCache
	26	EXPORT ArmDisableDataCache
	27	EXPORT ArmEnableInstructionCache
	28	EXPORT ArmDisableInstructionCache
	29	EXPORT ArmEnableBranchPrediction
	30	EXPORT ArmDisableBranchPrediction
	31
	32
	33	DC_ON EQU ( 0x1:SHL:2 )
	34	IC_ON EQU ( 0x1:SHL:12 )
	35
	36	AREA ArmCacheLib, CODE, READONLY
	37	PRESERVE8
	38
	39
	40	ArmInvalidateDataCacheEntryByMVA
	41	MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
	42	BX lr
	43
	44
	45	ArmCleanDataCacheEntryByMVA
	46	MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
	47	BX lr
	48
	49
	50	ArmCleanInvalidateDataCacheEntryByMVA
	51	MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
	52	BX lr
	53
	54	ArmEnableInstructionCache
	55	LDR R1,=IC_ON
	56	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	57	ORR R0,R0,R1 ;Set I bit
	58	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	59	BX LR
	60
	61	ArmDisableInstructionCache
	62	LDR R1,=IC_ON
	63	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	64	BIC R0,R0,R1 ;Clear I bit.
	65	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	66	BX LR
	67
	68	ArmInvalidateInstructionCache
	69	MOV R0,#0
	70	MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
	71	MOV R0,#0
	72	MCR p15,0,R0,c7,c10,4 ;Drain write buffer
	73	BX LR
	74
	75	ArmEnableMmu
	76	mrc p15,0,R0,c1,c0,0
	77	orr R0,R0,#1
	78	mcr p15,0,R0,c1,c0,0
	79	bx LR
	80
c2b5ca8b A	81	ArmMmuEnabled
	82	mrc p15,0,R0,c1,c0,0
	83	and R0,R0,#1
	84	bx LR
	85
2ef2b01e A	86	ArmDisableMmu
	87	mrc p15,0,R0,c1,c0,0
	88	bic R0,R0,#1
	89	mcr p15,0,R0,c1,c0,0
	90	mov R0,#0
	91	mcr p15,0,R0,c7,c10,4 ;Drain write buffer
	92	bx LR
	93
	94	ArmEnableDataCache
	95	LDR R1,=DC_ON
	96	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	97	ORR R0,R0,R1 ;Set C bit
	98	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	99	BX LR
	100
	101	ArmDisableDataCache
	102	LDR R1,=DC_ON
	103	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	104	BIC R0,R0,R1 ;Clear C bit
	105	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	106	BX LR
	107
	108	ArmCleanDataCache
	109	MRC p15,0,r15,c7,c10,3
	110	BNE ArmCleanDataCache
	111	MOV R0,#0
	112	MCR p15,0,R0,c7,c10,4 ;Drain write buffer
	113	BX LR
	114
	115	ArmInvalidateDataCache
	116	MOV R0,#0
	117	MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
	118	MOV R0,#0
	119	MCR p15,0,R0,c7,c10,4 ;Drain write buffer
	120	BX LR
	121
	122	ArmCleanInvalidateDataCache
	123	MRC p15,0,r15,c7,c14,3
	124	BNE ArmCleanInvalidateDataCache
	125	MOV R0,#0
	126	MCR p15,0,R0,c7,c10,4 ;Drain write buffer
	127	BX LR
	128
	129	ArmEnableBranchPrediction
	130	bx LR ;Branch prediction is not supported.
	131
	132	ArmDisableBranchPrediction
	133	bx LR ;Branch prediction is not supported.
	134
	135	END