[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm9 / Arm9Support.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmCleanInvalidateDataCache
    EXPORT  ArmCleanDataCache
    EXPORT  ArmInvalidateDataCache
    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmMmuEnabled
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction
    EXPORT  ArmDataMemoryBarrier
    EXPORT  ArmDataSyncronizationBarrier
    EXPORT  ArmInstructionSynchronizationBarrier


DC_ON       EQU     ( 0x1:SHL:2 )
IC_ON       EQU     ( 0x1:SHL:12 )

    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8


ArmInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
  BX      lr


ArmCleanDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  BX      lr


ArmCleanInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  BX      lr

ArmEnableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  ORR     R0,R0,R1             ;Set I bit
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR
  
ArmDisableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  BIC     R0,R0,R1             ;Clear I bit.
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR

ArmInvalidateInstructionCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
  BX      LR

ArmEnableMmu
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  bx      LR

ArmMmuEnabled
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  bx      LR

ArmDisableMmu
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  mov     R0,#0
  mcr     p15,0,R0,c7,c10,4     ;Drain write buffer
  bx      LR

ArmEnableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR
    
ArmDisableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  BIC     R0,R0,R1              ;Clear C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR

ArmCleanDataCache
  MRC     p15,0,r15,c7,c10,3
  BNE     ArmCleanDataCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4\s\s    ;Drain write buffer
  BX      LR

ArmInvalidateDataCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
  BX      LR
  
ArmCleanInvalidateDataCache
  MRC     p15,0,r15,c7,c14,3
  BNE     ArmCleanInvalidateDataCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c10,4\s\s    ;Drain write buffer
  BX      LR

ArmEnableBranchPrediction
  bx      LR                    ;Branch prediction is not supported.

ArmDisableBranchPrediction
  bx      LR                    ;Branch prediction is not supported.

ASM_PFX(ArmDataMemoryBarrier):
  mov R0, #0
  mcr P15, #0, R0, C7, C10, #5  ; Check to see if this is correct
  bx      LR
  
ASM_PFX(ArmDataSyncronizationBarrier):
  mov R0, #0
  mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
  bx      LR
  
ASM_PFX(ArmInstructionSynchronizationBarrier):
  MOV R0, #0
  MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
  bx      LR

    END
Commit	Line	Data
2ef2b01e A	1	//------------------------------------------------------------------------------
2ef2b01e A	2	//
d6ebcab7	3	// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
2ef2b01e	4	//
d6ebcab7	5	// This program and the accompanying materials
2ef2b01e A	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmCleanInvalidateDataCache
	16	EXPORT ArmCleanDataCache
	17	EXPORT ArmInvalidateDataCache
	18	EXPORT ArmInvalidateInstructionCache
	19	EXPORT ArmInvalidateDataCacheEntryByMVA
	20	EXPORT ArmCleanDataCacheEntryByMVA
	21	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	22	EXPORT ArmEnableMmu
	23	EXPORT ArmDisableMmu
c2b5ca8b	24	EXPORT ArmMmuEnabled
2ef2b01e A	25	EXPORT ArmEnableDataCache
	26	EXPORT ArmDisableDataCache
	27	EXPORT ArmEnableInstructionCache
	28	EXPORT ArmDisableInstructionCache
	29	EXPORT ArmEnableBranchPrediction
	30	EXPORT ArmDisableBranchPrediction
4b9fa129	31	EXPORT ArmDataMemoryBarrier
	32	EXPORT ArmDataSyncronizationBarrier
	33	EXPORT ArmInstructionSynchronizationBarrier
2ef2b01e A	34
	35
	36	DC_ON EQU ( 0x1:SHL:2 )
	37	IC_ON EQU ( 0x1:SHL:12 )
	38
	39	AREA ArmCacheLib, CODE, READONLY
	40	PRESERVE8
	41
	42
	43	ArmInvalidateDataCacheEntryByMVA
	44	MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
	45	BX lr
	46
	47
	48	ArmCleanDataCacheEntryByMVA
	49	MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
	50	BX lr
	51
	52
	53	ArmCleanInvalidateDataCacheEntryByMVA
	54	MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
	55	BX lr
	56
	57	ArmEnableInstructionCache
	58	LDR R1,=IC_ON
	59	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	60	ORR R0,R0,R1 ;Set I bit
	61	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	62	BX LR
	63
	64	ArmDisableInstructionCache
	65	LDR R1,=IC_ON
	66	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	67	BIC R0,R0,R1 ;Clear I bit.
	68	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	69	BX LR
	70
	71	ArmInvalidateInstructionCache
	72	MOV R0,#0
	73	MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
	74	MOV R0,#0
	75	MCR p15,0,R0,c7,c10,4 ;Drain write buffer
	76	BX LR
	77
	78	ArmEnableMmu
	79	mrc p15,0,R0,c1,c0,0
	80	orr R0,R0,#1
	81	mcr p15,0,R0,c1,c0,0
	82	bx LR
	83
c2b5ca8b A	84	ArmMmuEnabled
	85	mrc p15,0,R0,c1,c0,0
	86	and R0,R0,#1
	87	bx LR
	88
2ef2b01e A	89	ArmDisableMmu
	90	mrc p15,0,R0,c1,c0,0
	91	bic R0,R0,#1
	92	mcr p15,0,R0,c1,c0,0
	93	mov R0,#0
	94	mcr p15,0,R0,c7,c10,4 ;Drain write buffer
	95	bx LR
	96
	97	ArmEnableDataCache
	98	LDR R1,=DC_ON
	99	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	100	ORR R0,R0,R1 ;Set C bit
	101	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	102	BX LR
	103
	104	ArmDisableDataCache
	105	LDR R1,=DC_ON
	106	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
	107	BIC R0,R0,R1 ;Clear C bit
	108	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
	109	BX LR
	110
	111	ArmCleanDataCache
	112	MRC p15,0,r15,c7,c10,3
	113	BNE ArmCleanDataCache
	114	MOV R0,#0
58b5d037	115	MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer
2ef2b01e A	116	BX LR
	117
	118	ArmInvalidateDataCache
	119	MOV R0,#0
	120	MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
	121	MOV R0,#0
	122	MCR p15,0,R0,c7,c10,4 ;Drain write buffer
	123	BX LR
	124
	125	ArmCleanInvalidateDataCache
	126	MRC p15,0,r15,c7,c14,3
	127	BNE ArmCleanInvalidateDataCache
	128	MOV R0,#0
58b5d037	129	MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer
2ef2b01e A	130	BX LR
	131
	132	ArmEnableBranchPrediction
	133	bx LR ;Branch prediction is not supported.
	134
	135	ArmDisableBranchPrediction
	136	bx LR ;Branch prediction is not supported.
	137
4b9fa129	138	ASM_PFX(ArmDataMemoryBarrier):
	139	mov R0, #0
	140	mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
	141	bx LR
	142
	143	ASM_PFX(ArmDataSyncronizationBarrier):
	144	mov R0, #0
	145	mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
	146	bx LR
	147
	148	ASM_PFX(ArmInstructionSynchronizationBarrier):
	149	MOV R0, #0
	150	MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
	151	bx LR
	152
2ef2b01e	153	END