[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmCortexA / ArmCortexASupport.asm

//------------------------------------------------------------------------------ 
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution.  The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------

    EXPORT  ArmInvalidateInstructionCache
    EXPORT  ArmInvalidateDataCacheEntryByMVA
    EXPORT  ArmCleanDataCacheEntryByMVA
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
    EXPORT  ArmInvalidateDataCacheEntryBySetWay
    EXPORT  ArmCleanDataCacheEntryBySetWay
    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
    EXPORT  ArmDrainWriteBuffer
    EXPORT  ArmEnableMmu
    EXPORT  ArmDisableMmu
    EXPORT  ArmEnableDataCache
    EXPORT  ArmDisableDataCache
    EXPORT  ArmEnableInstructionCache
    EXPORT  ArmDisableInstructionCache
    EXPORT  ArmEnableBranchPrediction
    EXPORT  ArmDisableBranchPrediction

DC_ON       EQU     ( 0x1:SHL:2 )
IC_ON       EQU     ( 0x1:SHL:12 )
XP_ON       EQU     ( 0x1:SHL:23 )


    AREA    ArmCacheLib, CODE, READONLY
    PRESERVE8


ArmInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
  BX      lr


ArmCleanDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
  BX      lr


ArmCleanInvalidateDataCacheEntryByMVA
  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  BX      lr


ArmInvalidateDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line		
  bx      lr


ArmCleanInvalidateDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line		
  bx      lr


ArmCleanDataCacheEntryBySetWay
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line		
  bx      lr


ArmDrainWriteBuffer
  mcr     p15, 0, r0, c7, c10, 4       ; Drain write buffer for sync
  bx      lr


ArmInvalidateInstructionCache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  MOV     R0,#0
  MCR     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
  BX      LR

ArmEnableMmu
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  bx      LR

ArmDisableMmu
  mov     R0,#0
  mcr     p15,0,R0,c13,c0,0     ;FCSE PID register must be cleared before disabling MMU
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0      ;Disable MMU
  mov     R0,#0
  mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
  bx      LR

ArmEnableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR
    
ArmDisableDataCache
  LDR     R1,=DC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  BIC     R0,R0,R1              ;Clear C bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR

ArmEnableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
  ORR     R0,R0,R1              ;Set I bit
  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
  BX      LR
  
ArmDisableInstructionCache
  LDR     R1,=IC_ON
  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
  BIC     R0,R0,R1             ;Clear I bit.
  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
  BX      LR

ArmEnableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

ArmDisableBranchPrediction
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  bx      LR

    END
Commit	Line	Data
2ef2b01e A	1	//------------------------------------------------------------------------------
	2	//
	3	// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	//
	5	// All rights reserved. This program and the accompanying materials
	6	// are licensed and made available under the terms and conditions of the BSD License
	7	// which accompanies this distribution. The full text of the license may be found at
	8	// http://opensource.org/licenses/bsd-license.php
	9	//
	10	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	//
	13	//------------------------------------------------------------------------------
	14
	15	EXPORT ArmInvalidateInstructionCache
	16	EXPORT ArmInvalidateDataCacheEntryByMVA
	17	EXPORT ArmCleanDataCacheEntryByMVA
	18	EXPORT ArmCleanInvalidateDataCacheEntryByMVA
	19	EXPORT ArmInvalidateDataCacheEntryBySetWay
	20	EXPORT ArmCleanDataCacheEntryBySetWay
	21	EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
	22	EXPORT ArmDrainWriteBuffer
	23	EXPORT ArmEnableMmu
	24	EXPORT ArmDisableMmu
	25	EXPORT ArmEnableDataCache
	26	EXPORT ArmDisableDataCache
	27	EXPORT ArmEnableInstructionCache
	28	EXPORT ArmDisableInstructionCache
	29	EXPORT ArmEnableBranchPrediction
	30	EXPORT ArmDisableBranchPrediction
	31
	32	DC_ON EQU ( 0x1:SHL:2 )
	33	IC_ON EQU ( 0x1:SHL:12 )
	34	XP_ON EQU ( 0x1:SHL:23 )
	35
	36
	37	AREA ArmCacheLib, CODE, READONLY
	38	PRESERVE8
	39
	40
	41	ArmInvalidateDataCacheEntryByMVA
	42	MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
	43	BX lr
	44
	45
	46	ArmCleanDataCacheEntryByMVA
	47	MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
	48	BX lr
	49
	50
	51	ArmCleanInvalidateDataCacheEntryByMVA
	52	MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
	53	BX lr
	54
	55
	56	ArmInvalidateDataCacheEntryBySetWay
	57	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
	58	bx lr
	59
	60
	61	ArmCleanInvalidateDataCacheEntryBySetWay
	62	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
	63	bx lr
	64
65
66	ArmCleanDataCacheEntryBySetWay
67	mcr p15, 0, r0, c7, c10, 2 ; Clean this line
68	bx lr
69
70
71	ArmDrainWriteBuffer
72	mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
73	bx lr
74
75
76	ArmInvalidateInstructionCache
77	MOV R0,#0
78	MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
79	MOV R0,#0
80	MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
81	BX LR
82
83	ArmEnableMmu
84	mrc p15,0,R0,c1,c0,0
85	orr R0,R0,#1
86	mcr p15,0,R0,c1,c0,0
87	bx LR
88
89	ArmDisableMmu
90	mov R0,#0
91	mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
92	mrc p15,0,R0,c1,c0,0
93	bic R0,R0,#1
94	mcr p15,0,R0,c1,c0,0 ;Disable MMU
95	mov R0,#0
96	mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
97	mov R0,#0
98	mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
99	bx LR
100
101	ArmEnableDataCache
102	LDR R1,=DC_ON
103	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
104	ORR R0,R0,R1 ;Set C bit
105	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
106	BX LR
107
108	ArmDisableDataCache
109	LDR R1,=DC_ON
110	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
111	BIC R0,R0,R1 ;Clear C bit
112	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
113	BX LR
114
115	ArmEnableInstructionCache
116	LDR R1,=IC_ON
117	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
118	ORR R0,R0,R1 ;Set I bit
119	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
120	BX LR
121
122	ArmDisableInstructionCache
123	LDR R1,=IC_ON
124	MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
125	BIC R0,R0,R1 ;Clear I bit.
126	MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
127	BX LR
128
129	ArmEnableBranchPrediction
130	mrc p15, 0, r0, c1, c0, 0
131	orr r0, r0, #0x00000800
132	mcr p15, 0, r0, c1, c0, 0
133	bx LR
134
135	ArmDisableBranchPrediction
136	mrc p15, 0, r0, c1, c0, 0
137	bic r0, r0, #0x00000800
138	mcr p15, 0, r0, c1, c0, 0
139	bx LR
140
141	END