projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ef2b01e | 1 | /** @file\r |
| cd9fb745 | 2 | ArmLibPrivate.h\r |
| 2ef2b01e | 3 | \r |
| cd9fb745 | 4 | Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r |
| d6ebcab7 | 5 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 2ef2b01e | 6 | \r |
| 4059386c | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 2ef2b01e A |
8 | \r |
| 9 | **/\r | |
| 10 | \r | |
| cc15a619 PG |
11 | #ifndef ARM_LIB_PRIVATE_H_\r |
| 12 | #define ARM_LIB_PRIVATE_H_\r | |
| 2ef2b01e | 13 | \r |
| 429309e0 MK |
14 | #define CACHE_SIZE_4_KB (3UL)\r |
| 15 | #define CACHE_SIZE_8_KB (4UL)\r | |
| 16 | #define CACHE_SIZE_16_KB (5UL)\r | |
| 17 | #define CACHE_SIZE_32_KB (6UL)\r | |
| 18 | #define CACHE_SIZE_64_KB (7UL)\r | |
| 19 | #define CACHE_SIZE_128_KB (8UL)\r | |
| 2ef2b01e A |
20 | \r |
| 21 | #define CACHE_ASSOCIATIVITY_DIRECT (0UL)\r | |
| 22 | #define CACHE_ASSOCIATIVITY_4_WAY (2UL)\r | |
| 23 | #define CACHE_ASSOCIATIVITY_8_WAY (3UL)\r | |
| 24 | \r | |
| 429309e0 MK |
25 | #define CACHE_PRESENT (0UL)\r |
| 26 | #define CACHE_NOT_PRESENT (1UL)\r | |
| 2ef2b01e A |
27 | \r |
| 28 | #define CACHE_LINE_LENGTH_32_BYTES (2UL)\r | |
| 29 | \r | |
| 30 | #define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)\r | |
| 31 | #define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)\r | |
| 32 | #define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)\r | |
| 33 | #define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)\r | |
| 34 | \r | |
| 429309e0 MK |
35 | #define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)\r |
| 36 | #define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)\r | |
| 2ef2b01e | 37 | \r |
| 429309e0 MK |
38 | #define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r |
| 39 | #define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r | |
| 40 | #define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r | |
| 41 | #define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r | |
| 2ef2b01e | 42 | \r |
| 429309e0 MK |
43 | #define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r |
| 44 | #define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r | |
| 45 | #define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r | |
| 46 | #define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r | |
| 2ef2b01e | 47 | \r |
| 429309e0 MK |
48 | #define CACHE_TYPE(x) (((x) >> 25) & 0x0F)\r |
| 49 | #define CACHE_TYPE_WRITE_BACK (0x0EUL)\r | |
| 2ef2b01e | 50 | \r |
| 429309e0 MK |
51 | #define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)\r |
| 52 | #define CACHE_ARCHITECTURE_UNIFIED (0UL)\r | |
| 53 | #define CACHE_ARCHITECTURE_SEPARATE (1UL)\r | |
| 2ef2b01e A |
54 | \r |
| 55 | VOID\r | |
| 56 | CPSRMaskInsert (\r | |
| 57 | IN UINT32 Mask,\r | |
| 58 | IN UINT32 Value\r | |
| 59 | );\r | |
| 60 | \r | |
| 61 | UINT32\r | |
| 62 | CPSRRead (\r | |
| 63 | VOID\r | |
| 64 | );\r | |
| 65 | \r | |
| cc15a619 | 66 | #endif // ARM_LIB_PRIVATE_H_\r |