[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmLibSupport.S

#------------------------------------------------------------------------------ 
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution.  The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------

.text
.align 2
.globl ASM_PFX(Cp15IdCode)
.globl ASM_PFX(Cp15CacheInfo)
.globl ASM_PFX(ArmEnableInterrupts)
.globl ASM_PFX(ArmDisableInterrupts)
.globl ASM_PFX(ArmGetInterruptState)
.globl ASM_PFX(ArmEnableFiq)
.globl ASM_PFX(ArmDisableFiq)
.globl ASM_PFX(ArmGetFiqState)
.globl ASM_PFX(ArmInvalidateTlb)
.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
.globl ASM_PFX(ArmSetDomainAccessControl)
.globl ASM_PFX(CPSRMaskInsert)
.globl ASM_PFX(CPSRRead)
.globl ASM_PFX(ReadCCSIDR)
.globl ASM_PFX(ReadCLIDR)


#------------------------------------------------------------------------------

ASM_PFX(Cp15IdCode):
  mrc     p15,0,R0,c0,c0,0
  bx      LR

ASM_PFX(Cp15CacheInfo):
  mrc     p15,0,R0,c0,c0,1
  bx      LR

ASM_PFX(ArmEnableInterrupts):
  cpsie   i
	bx      LR

ASM_PFX(ArmDisableInterrupts):
  cpsid   i
	bx      LR

ASM_PFX(ArmGetInterruptState):
	mrs     R0,CPSR
	tst     R0,#0x80	    @Check if IRQ is enabled.
	moveq   R0,#1
	movne   R0,#0
	bx      LR

ASM_PFX(ArmEnableFiq):
  cpsie   f
	bx      LR

ASM_PFX(ArmDisableFiq):
  cpsid   f
	bx      LR

ASM_PFX(ArmGetFiqState):
	mrs     R0,CPSR
	tst     R0,#0x30	    @Check if IRQ is enabled.
	moveq   R0,#1
	movne   R0,#0
	bx      LR

ASM_PFX(ArmInvalidateTlb):
  mov     r0,#0
  mcr     p15,0,r0,c8,c7,0
  isb
  bx      lr

ASM_PFX(ArmSetTranslationTableBaseAddress):
  mcr     p15,0,r0,c2,c0,0
  isb
  bx      lr

ASM_PFX(ArmGetTranslationTableBaseAddress):
  mrc     p15,0,r0,c2,c0,0
  bx      lr


ASM_PFX(ArmSetDomainAccessControl):
  mcr     p15,0,r0,c3,c0,0
  isb
  bx      lr

ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
  stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  mov     r3, sp            @ copy the stack pointer into a non-banked register
  mrs     r2, cpsr          @ read the cpsr
  bic     r2, r2, r0        @ clear mask in the cpsr
  and     r1, r1, r0        @ clear bits outside the mask in the input
  orr     r2, r2, r1        @ set field
  msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  mov     sp, r3            @ restore stack pointer
  ldmfd   sp!, {r4-r12, lr} @ restore registers
  bx      lr                @ return (hopefully thumb-safe!)

ASM_PFX(CPSRRead):
  mrs     r0, cpsr
  bx      lr
  
ASM_PFX(ReadCCSIDR):
  mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
  isb
  mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
  bx  lr
  

ASM_PFX(ReadCLIDR):
  mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register

ASM_FUNCTION_REMOVE_IF_UNREFERENCED
Commit	Line	Data
1a27eb48	1	#------------------------------------------------------------------------------
	2	#
	3	# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	#
	5	# All rights reserved. This program and the accompanying materials
	6	# are licensed and made available under the terms and conditions of the BSD License
	7	# which accompanies this distribution. The full text of the license may be found at
	8	# http://opensource.org/licenses/bsd-license.php
	9	#
	10	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	#
	13	#------------------------------------------------------------------------------
	14
	15	.text
	16	.align 2
	17	.globl ASM_PFX(Cp15IdCode)
	18	.globl ASM_PFX(Cp15CacheInfo)
	19	.globl ASM_PFX(ArmEnableInterrupts)
	20	.globl ASM_PFX(ArmDisableInterrupts)
	21	.globl ASM_PFX(ArmGetInterruptState)
0416278c	22	.globl ASM_PFX(ArmEnableFiq)
	23	.globl ASM_PFX(ArmDisableFiq)
	24	.globl ASM_PFX(ArmGetFiqState)
1a27eb48	25	.globl ASM_PFX(ArmInvalidateTlb)
	26	.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
	27	.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
	28	.globl ASM_PFX(ArmSetDomainAccessControl)
	29	.globl ASM_PFX(CPSRMaskInsert)
	30	.globl ASM_PFX(CPSRRead)
98bc0c8c	31	.globl ASM_PFX(ReadCCSIDR)
	32	.globl ASM_PFX(ReadCLIDR)
	33
1a27eb48	34
	35	#------------------------------------------------------------------------------
	36
	37	ASM_PFX(Cp15IdCode):
	38	mrc p15,0,R0,c0,c0,0
	39	bx LR
	40
	41	ASM_PFX(Cp15CacheInfo):
	42	mrc p15,0,R0,c0,c0,1
	43	bx LR
	44
	45	ASM_PFX(ArmEnableInterrupts):
98bc0c8c	46	cpsie i
1a27eb48	47	bx LR
	48
	49	ASM_PFX(ArmDisableInterrupts):
98bc0c8c	50	cpsid i
1a27eb48	51	bx LR
	52
	53	ASM_PFX(ArmGetInterruptState):
	54	mrs R0,CPSR
	55	tst R0,#0x80 @Check if IRQ is enabled.
	56	moveq R0,#1
	57	movne R0,#0
	58	bx LR
	59
0416278c	60	ASM_PFX(ArmEnableFiq):
	61	cpsie f
	62	bx LR
	63
	64	ASM_PFX(ArmDisableFiq):
	65	cpsid f
	66	bx LR
	67
	68	ASM_PFX(ArmGetFiqState):
	69	mrs R0,CPSR
	70	tst R0,#0x30 @Check if IRQ is enabled.
	71	moveq R0,#1
	72	movne R0,#0
	73	bx LR
	74
1a27eb48	75	ASM_PFX(ArmInvalidateTlb):
	76	mov r0,#0
	77	mcr p15,0,r0,c8,c7,0
98bc0c8c	78	isb
1a27eb48	79	bx lr
	80
	81	ASM_PFX(ArmSetTranslationTableBaseAddress):
	82	mcr p15,0,r0,c2,c0,0
98bc0c8c	83	isb
1a27eb48	84	bx lr
	85
	86	ASM_PFX(ArmGetTranslationTableBaseAddress):
	87	mrc p15,0,r0,c2,c0,0
	88	bx lr
	89
	90
	91	ASM_PFX(ArmSetDomainAccessControl):
	92	mcr p15,0,r0,c3,c0,0
98bc0c8c	93	isb
1a27eb48	94	bx lr
	95
	96	ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
	97	stmfd sp!, {r4-r12, lr} @ save all the banked registers
	98	mov r3, sp @ copy the stack pointer into a non-banked register
	99	mrs r2, cpsr @ read the cpsr
	100	bic r2, r2, r0 @ clear mask in the cpsr
	101	and r1, r1, r0 @ clear bits outside the mask in the input
	102	orr r2, r2, r1 @ set field
	103	msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
	104	mov sp, r3 @ restore stack pointer
	105	ldmfd sp!, {r4-r12, lr} @ restore registers
	106	bx lr @ return (hopefully thumb-safe!)
	107
	108	ASM_PFX(CPSRRead):
	109	mrs r0, cpsr
	110	bx lr
	111
98bc0c8c	112	ASM_PFX(ReadCCSIDR):
	113	mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
	114	isb
	115	mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
	116	bx lr
	117
	118
	119	ASM_PFX(ReadCLIDR):
	120	mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
	121
1a27eb48	122	ASM_FUNCTION_REMOVE_IF_UNREFERENCED