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1a27eb48 | 1 | #------------------------------------------------------------------------------ |
2 | # | |
d6ebcab7 | 3 | # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> |
1a27eb48 | 4 | # |
d6ebcab7 | 5 | # This program and the accompanying materials |
1a27eb48 | 6 | # are licensed and made available under the terms and conditions of the BSD License |
7 | # which accompanies this distribution. The full text of the license may be found at | |
8 | # http://opensource.org/licenses/bsd-license.php | |
9 | # | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | # | |
13 | #------------------------------------------------------------------------------ | |
14 | ||
1bfda055 | 15 | #include <AsmMacroIoLib.h> |
98bc0c8c | 16 | |
bb02cb80 | 17 | .text |
18 | .align 2 | |
1a27eb48 | 19 | |
1bfda055 | 20 | GCC_ASM_EXPORT(Cp15IdCode) |
21 | GCC_ASM_EXPORT(Cp15CacheInfo) | |
22 | GCC_ASM_EXPORT(ArmIsMPCore) | |
23 | GCC_ASM_EXPORT(ArmEnableAsynchronousAbort) | |
24 | GCC_ASM_EXPORT(ArmDisableAsynchronousAbort) | |
25 | GCC_ASM_EXPORT(ArmEnableIrq) | |
26 | GCC_ASM_EXPORT(ArmDisableIrq) | |
27 | GCC_ASM_EXPORT(ArmGetInterruptState) | |
28 | GCC_ASM_EXPORT(ArmEnableFiq) | |
29 | GCC_ASM_EXPORT(ArmDisableFiq) | |
30 | GCC_ASM_EXPORT(ArmEnableInterrupts) | |
31 | GCC_ASM_EXPORT(ArmDisableInterrupts) | |
32 | GCC_ASM_EXPORT(ArmGetFiqState) | |
33 | GCC_ASM_EXPORT(ArmInvalidateTlb) | |
34 | GCC_ASM_EXPORT(ArmSetTTBR0) | |
35 | GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) | |
36 | GCC_ASM_EXPORT(ArmSetDomainAccessControl) | |
37 | GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry) | |
38 | GCC_ASM_EXPORT(CPSRMaskInsert) | |
39 | GCC_ASM_EXPORT(CPSRRead) | |
40 | GCC_ASM_EXPORT(ReadCCSIDR) | |
41 | GCC_ASM_EXPORT(ReadCLIDR) | |
42 | ||
43 | ||
44 | ||
1a27eb48 | 45 | #------------------------------------------------------------------------------ |
46 | ||
47 | ASM_PFX(Cp15IdCode): | |
48 | mrc p15,0,R0,c0,c0,0 | |
49 | bx LR | |
50 | ||
51 | ASM_PFX(Cp15CacheInfo): | |
52 | mrc p15,0,R0,c0,c0,1 | |
53 | bx LR | |
54 | ||
1bfda055 | 55 | ASM_PFX(ArmIsMPCore): |
56 | mrc p15,0,R0,c0,c0,5 | |
57 | // Get Multiprocessing extension (bit31) & U bit (bit30) | |
58 | and R0, R0, #0xC0000000 | |
59 | // if bit30 == 0 then the processor is part of a multiprocessor system) | |
60 | and R0, R0, #0x80000000 | |
61 | bx LR | |
62 | ||
63 | ASM_PFX(ArmEnableAsynchronousAbort): | |
64 | cpsie a | |
65 | isb | |
66 | bx LR | |
67 | ||
68 | ASM_PFX(ArmDisableAsynchronousAbort): | |
69 | cpsid a | |
70 | isb | |
71 | bx LR | |
72 | ||
73 | ASM_PFX(ArmEnableIrq): | |
98bc0c8c | 74 | cpsie i |
1bfda055 | 75 | isb |
76 | bx LR | |
1a27eb48 | 77 | |
1bfda055 | 78 | ASM_PFX(ArmDisableIrq): |
98bc0c8c | 79 | cpsid i |
1bfda055 | 80 | isb |
81 | bx LR | |
1a27eb48 | 82 | |
83 | ASM_PFX(ArmGetInterruptState): | |
1bfda055 | 84 | mrs R0,CPSR |
85 | tst R0,#0x80 @Check if IRQ is enabled. | |
86 | moveq R0,#1 | |
87 | movne R0,#0 | |
88 | bx LR | |
1a27eb48 | 89 | |
0416278c | 90 | ASM_PFX(ArmEnableFiq): |
91 | cpsie f | |
1bfda055 | 92 | isb |
93 | bx LR | |
0416278c | 94 | |
95 | ASM_PFX(ArmDisableFiq): | |
96 | cpsid f | |
1bfda055 | 97 | isb |
98 | bx LR | |
99 | ||
100 | ASM_PFX(ArmEnableInterrupts): | |
101 | cpsie if | |
102 | isb | |
103 | bx LR | |
104 | ||
105 | ASM_PFX(ArmDisableInterrupts): | |
106 | cpsid if | |
107 | isb | |
108 | bx LR | |
0416278c | 109 | |
110 | ASM_PFX(ArmGetFiqState): | |
1bfda055 | 111 | mrs R0,CPSR |
112 | tst R0,#0x40 @Check if FIQ is enabled. | |
113 | moveq R0,#1 | |
114 | movne R0,#0 | |
115 | bx LR | |
0416278c | 116 | |
1a27eb48 | 117 | ASM_PFX(ArmInvalidateTlb): |
118 | mov r0,#0 | |
119 | mcr p15,0,r0,c8,c7,0 | |
bb02cb80 | 120 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp |
121 | dsb | |
98bc0c8c | 122 | isb |
1a27eb48 | 123 | bx lr |
124 | ||
1bfda055 | 125 | ASM_PFX(ArmSetTTBR0): |
1a27eb48 | 126 | mcr p15,0,r0,c2,c0,0 |
98bc0c8c | 127 | isb |
1a27eb48 | 128 | bx lr |
129 | ||
1bfda055 | 130 | ASM_PFX(ArmGetTTBR0BaseAddress): |
1a27eb48 | 131 | mrc p15,0,r0,c2,c0,0 |
1bfda055 | 132 | LoadConstantToReg(0xFFFFC000, r1) |
133 | and r0, r0, r1 | |
bb02cb80 | 134 | isb |
1a27eb48 | 135 | bx lr |
136 | ||
137 | ||
138 | ASM_PFX(ArmSetDomainAccessControl): | |
139 | mcr p15,0,r0,c3,c0,0 | |
98bc0c8c | 140 | isb |
1a27eb48 | 141 | bx lr |
142 | ||
bb02cb80 | 143 | // |
144 | //VOID | |
145 | //ArmUpdateTranslationTableEntry ( | |
146 | // IN VOID *TranslationTableEntry // R0 | |
147 | // IN VOID *MVA // R1 | |
148 | // ); | |
149 | ASM_PFX(ArmUpdateTranslationTableEntry): | |
150 | mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA | |
151 | dsb | |
152 | mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA | |
153 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp | |
154 | dsb | |
155 | isb | |
156 | bx lr | |
157 | ||
1a27eb48 | 158 | ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert |
159 | stmfd sp!, {r4-r12, lr} @ save all the banked registers | |
160 | mov r3, sp @ copy the stack pointer into a non-banked register | |
161 | mrs r2, cpsr @ read the cpsr | |
162 | bic r2, r2, r0 @ clear mask in the cpsr | |
163 | and r1, r1, r0 @ clear bits outside the mask in the input | |
164 | orr r2, r2, r1 @ set field | |
165 | msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) | |
bb02cb80 | 166 | isb |
1a27eb48 | 167 | mov sp, r3 @ restore stack pointer |
168 | ldmfd sp!, {r4-r12, lr} @ restore registers | |
169 | bx lr @ return (hopefully thumb-safe!) | |
170 | ||
171 | ASM_PFX(CPSRRead): | |
172 | mrs r0, cpsr | |
173 | bx lr | |
174 | ||
bb02cb80 | 175 | // UINT32 |
176 | // ReadCCSIDR ( | |
177 | // IN UINT32 CSSELR | |
178 | // ) | |
98bc0c8c | 179 | ASM_PFX(ReadCCSIDR): |
180 | mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) | |
181 | isb | |
182 | mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR) | |
183 | bx lr | |
184 | ||
bb02cb80 | 185 | // UINT32 |
186 | // ReadCLIDR ( | |
187 | // IN UINT32 CSSELR | |
188 | // ) | |
98bc0c8c | 189 | ASM_PFX(ReadCLIDR): |
190 | mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register | |
bb02cb80 | 191 | bx lr |
98bc0c8c | 192 | |
1a27eb48 | 193 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED |