projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3402aac7 | 1 | #------------------------------------------------------------------------------\r |
| bd6b9799 | 2 | #\r |
| 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| d6dc67ba | 4 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
| 0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
| bd6b9799 | 6 | #\r |
| 7 | # This program and the accompanying materials\r | |
| 8 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 9 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 10 | # http://opensource.org/licenses/bsd-license.php\r | |
| 11 | #\r | |
| 12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 14 | #\r | |
| 15 | #------------------------------------------------------------------------------\r | |
| 16 | \r | |
| 17 | #include <AsmMacroIoLib.h>\r | |
| 18 | \r | |
| 0efaa42f | 19 | ASM_FUNC(ArmIsMpCore)\r |
| bd6b9799 | 20 | mrc p15,0,R0,c0,c0,5\r |
| 21 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r | |
| 22 | and R0, R0, #0xC0000000\r | |
| 5a539eb5 OM |
23 | // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system\r |
| 24 | cmp R0, #0x80000000\r | |
| 25 | moveq R0, #1\r | |
| 26 | movne R0, #0\r | |
| bd6b9799 | 27 | bx LR\r |
| 28 | \r | |
| 0efaa42f | 29 | ASM_FUNC(ArmEnableAsynchronousAbort)\r |
| bd6b9799 | 30 | cpsie a\r |
| 31 | isb\r | |
| 32 | bx LR\r | |
| 33 | \r | |
| 0efaa42f | 34 | ASM_FUNC(ArmDisableAsynchronousAbort)\r |
| bd6b9799 | 35 | cpsid a\r |
| 36 | isb\r | |
| 37 | bx LR\r | |
| 38 | \r | |
| 0efaa42f | 39 | ASM_FUNC(ArmEnableIrq)\r |
| bd6b9799 | 40 | cpsie i\r |
| 41 | isb\r | |
| 42 | bx LR\r | |
| 43 | \r | |
| 0efaa42f | 44 | ASM_FUNC(ArmDisableIrq)\r |
| bd6b9799 | 45 | cpsid i\r |
| 46 | isb\r | |
| 47 | bx LR\r | |
| 48 | \r | |
| 0efaa42f | 49 | ASM_FUNC(ArmEnableFiq)\r |
| bd6b9799 | 50 | cpsie f\r |
| 51 | isb\r | |
| 52 | bx LR\r | |
| 53 | \r | |
| 0efaa42f | 54 | ASM_FUNC(ArmDisableFiq)\r |
| bd6b9799 | 55 | cpsid f\r |
| 56 | isb\r | |
| 57 | bx LR\r | |
| 58 | \r | |
| 0efaa42f | 59 | ASM_FUNC(ArmEnableInterrupts)\r |
| bd6b9799 | 60 | cpsie if\r |
| 61 | isb\r | |
| 62 | bx LR\r | |
| 63 | \r | |
| 0efaa42f | 64 | ASM_FUNC(ArmDisableInterrupts)\r |
| bd6b9799 | 65 | cpsid if\r |
| 66 | isb\r | |
| 67 | bx LR\r | |
| 3402aac7 RC |
68 | \r |
| 69 | // UINT32\r | |
| bd6b9799 | 70 | // ReadCCSIDR (\r |
| 71 | // IN UINT32 CSSELR\r | |
| 3402aac7 | 72 | // )\r |
| 0efaa42f | 73 | ASM_FUNC(ReadCCSIDR)\r |
| bd6b9799 | 74 | mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)\r |
| 75 | isb\r | |
| 76 | mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)\r | |
| 77 | bx lr\r | |
| 3402aac7 RC |
78 | \r |
| 79 | // UINT32\r | |
| bd6b9799 | 80 | // ReadCLIDR (\r |
| 81 | // IN UINT32 CSSELR\r | |
| 3402aac7 | 82 | // )\r |
| 0efaa42f | 83 | ASM_FUNC(ReadCLIDR)\r |
| bd6b9799 | 84 | mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register\r |
| 85 | bx lr\r | |
| 86 | \r | |
| 0efaa42f | 87 | ASM_FUNC(ArmReadNsacr)\r |
| d6dc67ba OM |
88 | mrc p15, 0, r0, c1, c1, 2\r |
| 89 | bx lr\r | |
| 90 | \r | |
| 0efaa42f | 91 | ASM_FUNC(ArmWriteNsacr)\r |
| d6dc67ba OM |
92 | mcr p15, 0, r0, c1, c1, 2\r |
| 93 | bx lr\r | |
| 94 | \r | |
| bd6b9799 | 95 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |