projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| bd6b9799 | 1 | //------------------------------------------------------------------------------ \r |
| 2 | //\r | |
| 3 | // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
| d6dc67ba | 4 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
| bd6b9799 | 5 | //\r |
| 6 | // This program and the accompanying materials\r | |
| 7 | // are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | // which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | // http://opensource.org/licenses/bsd-license.php\r | |
| 10 | //\r | |
| 11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | //\r | |
| 14 | //------------------------------------------------------------------------------\r | |
| 15 | \r | |
| 16 | \r | |
| 17 | EXPORT ArmIsMpCore\r | |
| 18 | EXPORT ArmEnableAsynchronousAbort\r | |
| 19 | EXPORT ArmDisableAsynchronousAbort\r | |
| 20 | EXPORT ArmEnableIrq\r | |
| 21 | EXPORT ArmDisableIrq\r | |
| 22 | EXPORT ArmEnableFiq\r | |
| 23 | EXPORT ArmDisableFiq\r | |
| 24 | EXPORT ArmEnableInterrupts\r | |
| 25 | EXPORT ArmDisableInterrupts\r | |
| 26 | EXPORT ReadCCSIDR\r | |
| 27 | EXPORT ReadCLIDR\r | |
| d6dc67ba OM |
28 | EXPORT ArmReadNsacr\r |
| 29 | EXPORT ArmWriteNsacr\r | |
| 30 | \r | |
| bd6b9799 | 31 | AREA ArmLibSupportV7, CODE, READONLY\r |
| 32 | \r | |
| 33 | \r | |
| 34 | //------------------------------------------------------------------------------\r | |
| 35 | \r | |
| 36 | ArmIsMpCore\r | |
| 37 | mrc p15,0,R0,c0,c0,5\r | |
| 38 | // Get Multiprocessing extension (bit31) & U bit (bit30)\r | |
| 39 | and R0, R0, #0xC0000000\r | |
| 40 | // if bit30 == 0 then the processor is part of a multiprocessor system)\r | |
| 41 | and R0, R0, #0x80000000\r | |
| 42 | bx LR\r | |
| 43 | \r | |
| 44 | ArmEnableAsynchronousAbort\r | |
| 45 | cpsie a\r | |
| 46 | isb\r | |
| 47 | bx LR\r | |
| 48 | \r | |
| 49 | ArmDisableAsynchronousAbort\r | |
| 50 | cpsid a\r | |
| 51 | isb\r | |
| 52 | bx LR\r | |
| 53 | \r | |
| 54 | ArmEnableIrq\r | |
| 55 | cpsie i\r | |
| 56 | isb\r | |
| 57 | bx LR\r | |
| 58 | \r | |
| 59 | ArmDisableIrq\r | |
| 60 | cpsid i\r | |
| 61 | isb\r | |
| 62 | bx LR\r | |
| 63 | \r | |
| 64 | ArmEnableFiq\r | |
| 65 | cpsie f\r | |
| 66 | isb\r | |
| 67 | bx LR\r | |
| 68 | \r | |
| 69 | ArmDisableFiq\r | |
| 70 | cpsid f\r | |
| 71 | isb\r | |
| 72 | bx LR\r | |
| 73 | \r | |
| 74 | ArmEnableInterrupts\r | |
| 75 | cpsie if\r | |
| 76 | isb\r | |
| 77 | bx LR\r | |
| 78 | \r | |
| 79 | ArmDisableInterrupts\r | |
| 80 | cpsid if\r | |
| 81 | isb\r | |
| 82 | bx LR\r | |
| 83 | \r | |
| 84 | // UINT32 \r | |
| 85 | // ReadCCSIDR (\r | |
| 86 | // IN UINT32 CSSELR\r | |
| 87 | // ) \r | |
| 88 | ReadCCSIDR\r | |
| 89 | mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)\r | |
| 90 | isb\r | |
| 91 | mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)\r | |
| 92 | bx lr\r | |
| 93 | \r | |
| 94 | // UINT32 \r | |
| 95 | // ReadCLIDR (\r | |
| 96 | // IN UINT32 CSSELR\r | |
| 97 | // ) \r | |
| 98 | ReadCLIDR\r | |
| 99 | mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register\r | |
| 100 | bx lr\r | |
| d6dc67ba OM |
101 | \r |
| 102 | ArmReadNsacr\r | |
| 103 | mrc p15, 0, r0, c1, c1, 2\r | |
| 104 | bx lr\r | |
| 105 | \r | |
| 106 | ArmWriteNsacr\r | |
| 107 | mcr p15, 0, r0, c1, c1, 2\r | |
| 108 | bx lr\r | |
| 109 | \r | |
| 2575b726 | 110 | END\r |