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1e57a462 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
4 | * \r | |
5 | * This program and the accompanying materials \r | |
6 | * are licensed and made available under the terms and conditions of the BSD License \r | |
7 | * which accompanies this distribution. The full text of the license may be found at \r | |
8 | * http://opensource.org/licenses/bsd-license.php \r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Uefi.h> \r | |
16 | #include <Chipset/ArmV7.h>\r | |
17 | #include <Library/BaseMemoryLib.h>\r | |
18 | #include <Library/MemoryAllocationLib.h>\r | |
19 | #include <Library/ArmLib.h>\r | |
20 | #include <Library/BaseLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include "ArmV7Lib.h"\r | |
23 | #include "ArmLibPrivate.h"\r | |
24 | #include <Library/ArmV7ArchTimerLib.h>\r | |
25 | \r | |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | ArmArchTimerReadReg (\r | |
29 | IN ARM_ARCH_TIMER_REGS Reg,\r | |
30 | OUT VOID *DstBuf\r | |
31 | )\r | |
32 | {\r | |
33 | // Check if the Generic/Architecture timer is implemented\r | |
34 | if (ArmIsArchTimerImplemented ()) {\r | |
35 | \r | |
36 | switch (Reg) {\r | |
37 | \r | |
38 | case CntFrq:\r | |
39 | *((UINTN *)DstBuf) = ArmReadCntFrq ();\r | |
40 | break;\r | |
41 | \r | |
42 | case CntPct:\r | |
43 | *((UINT64 *)DstBuf) = ArmReadCntPct ();\r | |
44 | break;\r | |
45 | \r | |
46 | case CntkCtl:\r | |
47 | *((UINTN *)DstBuf) = ArmReadCntkCtl();\r | |
48 | break;\r | |
49 | \r | |
50 | case CntpTval:\r | |
51 | *((UINTN *)DstBuf) = ArmReadCntpTval ();\r | |
52 | break;\r | |
53 | \r | |
54 | case CntpCtl:\r | |
55 | *((UINTN *)DstBuf) = ArmReadCntpCtl ();\r | |
56 | break;\r | |
57 | \r | |
58 | case CntvTval:\r | |
59 | *((UINTN *)DstBuf) = ArmReadCntvTval ();\r | |
60 | break;\r | |
61 | \r | |
62 | case CntvCtl:\r | |
63 | *((UINTN *)DstBuf) = ArmReadCntvCtl ();\r | |
64 | break;\r | |
65 | \r | |
66 | case CntvCt:\r | |
67 | *((UINT64 *)DstBuf) = ArmReadCntvCt ();\r | |
68 | break;\r | |
69 | \r | |
70 | case CntpCval:\r | |
71 | *((UINT64 *)DstBuf) = ArmReadCntpCval ();\r | |
72 | break;\r | |
73 | \r | |
74 | case CntvCval:\r | |
75 | *((UINT64 *)DstBuf) = ArmReadCntvCval ();\r | |
76 | break;\r | |
77 | \r | |
78 | case CntvOff:\r | |
79 | *((UINT64 *)DstBuf) = ArmReadCntvOff ();\r | |
80 | break;\r | |
81 | \r | |
82 | case CnthCtl:\r | |
83 | case CnthpTval:\r | |
84 | case CnthpCtl:\r | |
85 | case CnthpCval:\r | |
86 | DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r | |
87 | break;\r | |
88 | \r | |
89 | default:\r | |
90 | DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r | |
91 | }\r | |
92 | } else {\r | |
93 | DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r | |
94 | ASSERT (0);\r | |
95 | }\r | |
96 | }\r | |
97 | \r | |
98 | VOID\r | |
99 | EFIAPI\r | |
100 | ArmArchTimerWriteReg (\r | |
101 | IN ARM_ARCH_TIMER_REGS Reg,\r | |
102 | IN VOID *SrcBuf\r | |
103 | )\r | |
104 | {\r | |
105 | // Check if the Generic/Architecture timer is implemented\r | |
106 | if (ArmIsArchTimerImplemented ()) {\r | |
107 | \r | |
108 | switch (Reg) {\r | |
109 | \r | |
110 | case CntFrq:\r | |
111 | ArmWriteCntFrq (*((UINTN *)SrcBuf));\r | |
112 | break;\r | |
113 | \r | |
114 | case CntPct:\r | |
115 | DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));\r | |
116 | break;\r | |
117 | \r | |
118 | case CntkCtl:\r | |
119 | ArmWriteCntkCtl (*((UINTN *)SrcBuf));\r | |
120 | break;\r | |
121 | \r | |
122 | case CntpTval:\r | |
123 | ArmWriteCntpTval (*((UINTN *)SrcBuf));\r | |
124 | break;\r | |
125 | \r | |
126 | case CntpCtl:\r | |
127 | ArmWriteCntpCtl (*((UINTN *)SrcBuf));\r | |
128 | break;\r | |
129 | \r | |
130 | case CntvTval:\r | |
131 | ArmWriteCntvTval (*((UINTN *)SrcBuf));\r | |
132 | break;\r | |
133 | \r | |
134 | case CntvCtl:\r | |
135 | ArmWriteCntvCtl (*((UINTN *)SrcBuf));\r | |
136 | break;\r | |
137 | \r | |
138 | case CntvCt:\r | |
139 | DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));\r | |
140 | break;\r | |
141 | \r | |
142 | case CntpCval:\r | |
143 | ArmWriteCntpCval (*((UINT64 *)SrcBuf) );\r | |
144 | break;\r | |
145 | \r | |
146 | case CntvCval:\r | |
147 | ArmWriteCntvCval (*((UINT64 *)SrcBuf) );\r | |
148 | break;\r | |
149 | \r | |
150 | case CntvOff:\r | |
151 | ArmWriteCntvOff (*((UINT64 *)SrcBuf));\r | |
152 | break;\r | |
153 | \r | |
154 | case CnthCtl:\r | |
155 | case CnthpTval:\r | |
156 | case CnthpCtl:\r | |
157 | case CnthpCval:\r | |
158 | DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r | |
159 | break;\r | |
160 | \r | |
161 | default:\r | |
162 | DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r | |
163 | }\r | |
164 | } else {\r | |
165 | DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r | |
166 | ASSERT (0);\r | |
167 | }\r | |
168 | }\r | |
169 | \r | |
170 | VOID\r | |
171 | EFIAPI\r | |
172 | ArmArchTimerEnableTimer (\r | |
173 | VOID\r | |
174 | )\r | |
175 | {\r | |
176 | UINTN TimerCtrlReg;\r | |
177 | \r | |
178 | ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);\r | |
179 | TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r | |
180 | ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);\r | |
181 | }\r | |
182 | \r | |
183 | VOID\r | |
184 | EFIAPI\r | |
185 | ArmArchTimerDisableTimer (\r | |
186 | VOID\r | |
187 | )\r | |
188 | {\r | |
189 | UINTN TimerCtrlReg;\r | |
190 | \r | |
191 | ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);\r | |
192 | TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r | |
193 | ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);\r | |
194 | }\r | |
195 | \r | |
196 | VOID\r | |
197 | EFIAPI\r | |
198 | ArmArchTimerSetTimerFreq (\r | |
199 | IN UINTN FreqInHz\r | |
200 | )\r | |
201 | {\r | |
202 | ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);\r | |
203 | }\r | |
204 | \r | |
205 | UINTN\r | |
206 | EFIAPI\r | |
207 | ArmArchTimerGetTimerFreq (\r | |
208 | VOID\r | |
209 | )\r | |
210 | {\r | |
211 | UINTN ArchTimerFreq = 0;\r | |
212 | ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);\r | |
213 | return ArchTimerFreq;\r | |
214 | }\r | |
215 | \r | |
216 | UINTN\r | |
217 | EFIAPI\r | |
218 | ArmArchTimerGetTimerVal (\r | |
219 | VOID\r | |
220 | )\r | |
221 | {\r | |
222 | UINTN ArchTimerVal;\r | |
223 | ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);\r | |
224 | return ArchTimerVal;\r | |
225 | }\r | |
226 | \r | |
227 | \r | |
228 | VOID\r | |
229 | EFIAPI\r | |
230 | ArmArchTimerSetTimerVal (\r | |
231 | IN UINTN Val\r | |
232 | )\r | |
233 | {\r | |
234 | ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);\r | |
235 | }\r | |
236 | \r | |
237 | UINT64\r | |
238 | EFIAPI\r | |
239 | ArmArchTimerGetSystemCount (\r | |
240 | VOID\r | |
241 | )\r | |
242 | {\r | |
243 | UINT64 SystemCount;\r | |
244 | ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);\r | |
245 | return SystemCount;\r | |
246 | }\r | |
247 | \r | |
248 | UINTN\r | |
249 | EFIAPI\r | |
250 | ArmArchTimerGetTimerCtrlReg (\r | |
251 | VOID\r | |
252 | )\r | |
253 | {\r | |
254 | UINTN Val;\r | |
255 | ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);\r | |
256 | return Val;\r | |
257 | }\r | |
258 | \r | |
259 | VOID\r | |
260 | EFIAPI\r | |
261 | ArmArchTimerSetTimerCtrlReg (\r | |
262 | UINTN Val\r | |
263 | )\r | |
264 | {\r | |
265 | ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);\r | |
266 | }\r | |
267 | \r | |
268 | VOID\r | |
269 | EFIAPI\r | |
270 | ArmArchTimerSetCompareVal (\r | |
271 | IN UINT64 Val\r | |
272 | )\r | |
273 | {\r | |
274 | ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);\r | |
275 | }\r |