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1e57a462 | 1 | /** @file\r |
2 | *\r | |
992a1f83 | 3 | * Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
1e57a462 | 4 | *\r |
3402aac7 RC |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
1e57a462 | 12 | *\r |
13 | **/\r | |
14 | \r | |
992a1f83 | 15 | #include <Uefi.h>\r |
1e57a462 | 16 | #include <Chipset/ArmV7.h>\r |
17 | #include <Library/BaseMemoryLib.h>\r | |
1e57a462 | 18 | #include <Library/ArmLib.h>\r |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include "ArmV7Lib.h"\r | |
22 | #include "ArmLibPrivate.h"\r | |
d4bb43ce | 23 | #include <Library/ArmArchTimer.h>\r |
1e57a462 | 24 | \r |
25 | VOID\r | |
26 | EFIAPI\r | |
27 | ArmArchTimerReadReg (\r | |
28 | IN ARM_ARCH_TIMER_REGS Reg,\r | |
29 | OUT VOID *DstBuf\r | |
30 | )\r | |
31 | {\r | |
32 | // Check if the Generic/Architecture timer is implemented\r | |
33 | if (ArmIsArchTimerImplemented ()) {\r | |
1e57a462 | 34 | switch (Reg) {\r |
1e57a462 | 35 | case CntFrq:\r |
36 | *((UINTN *)DstBuf) = ArmReadCntFrq ();\r | |
992a1f83 | 37 | return;\r |
1e57a462 | 38 | \r |
39 | case CntPct:\r | |
40 | *((UINT64 *)DstBuf) = ArmReadCntPct ();\r | |
992a1f83 | 41 | return;\r |
1e57a462 | 42 | \r |
43 | case CntkCtl:\r | |
44 | *((UINTN *)DstBuf) = ArmReadCntkCtl();\r | |
992a1f83 | 45 | return;\r |
1e57a462 | 46 | \r |
47 | case CntpTval:\r | |
48 | *((UINTN *)DstBuf) = ArmReadCntpTval ();\r | |
992a1f83 | 49 | return;\r |
1e57a462 | 50 | \r |
51 | case CntpCtl:\r | |
52 | *((UINTN *)DstBuf) = ArmReadCntpCtl ();\r | |
992a1f83 | 53 | return;\r |
1e57a462 | 54 | \r |
55 | case CntvTval:\r | |
56 | *((UINTN *)DstBuf) = ArmReadCntvTval ();\r | |
992a1f83 | 57 | return;\r |
1e57a462 | 58 | \r |
59 | case CntvCtl:\r | |
60 | *((UINTN *)DstBuf) = ArmReadCntvCtl ();\r | |
992a1f83 | 61 | return;\r |
1e57a462 | 62 | \r |
63 | case CntvCt:\r | |
64 | *((UINT64 *)DstBuf) = ArmReadCntvCt ();\r | |
992a1f83 | 65 | return;\r |
1e57a462 | 66 | \r |
67 | case CntpCval:\r | |
68 | *((UINT64 *)DstBuf) = ArmReadCntpCval ();\r | |
992a1f83 | 69 | return;\r |
1e57a462 | 70 | \r |
71 | case CntvCval:\r | |
72 | *((UINT64 *)DstBuf) = ArmReadCntvCval ();\r | |
992a1f83 | 73 | return;\r |
1e57a462 | 74 | \r |
75 | case CntvOff:\r | |
76 | *((UINT64 *)DstBuf) = ArmReadCntvOff ();\r | |
992a1f83 | 77 | return;\r |
1e57a462 | 78 | \r |
79 | case CnthCtl:\r | |
80 | case CnthpTval:\r | |
81 | case CnthpCtl:\r | |
82 | case CnthpCval:\r | |
992a1f83 | 83 | DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r |
1e57a462 | 84 | break;\r |
85 | \r | |
86 | default:\r | |
87 | DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r | |
88 | }\r | |
89 | } else {\r | |
90 | DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r | |
91 | ASSERT (0);\r | |
92 | }\r | |
992a1f83 OM |
93 | \r |
94 | *((UINT64 *)DstBuf) = 0;\r | |
1e57a462 | 95 | }\r |
96 | \r | |
97 | VOID\r | |
98 | EFIAPI\r | |
99 | ArmArchTimerWriteReg (\r | |
100 | IN ARM_ARCH_TIMER_REGS Reg,\r | |
101 | IN VOID *SrcBuf\r | |
102 | )\r | |
103 | {\r | |
104 | // Check if the Generic/Architecture timer is implemented\r | |
105 | if (ArmIsArchTimerImplemented ()) {\r | |
106 | \r | |
107 | switch (Reg) {\r | |
108 | \r | |
109 | case CntFrq:\r | |
110 | ArmWriteCntFrq (*((UINTN *)SrcBuf));\r | |
111 | break;\r | |
112 | \r | |
113 | case CntPct:\r | |
114 | DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));\r | |
115 | break;\r | |
116 | \r | |
117 | case CntkCtl:\r | |
118 | ArmWriteCntkCtl (*((UINTN *)SrcBuf));\r | |
119 | break;\r | |
120 | \r | |
121 | case CntpTval:\r | |
122 | ArmWriteCntpTval (*((UINTN *)SrcBuf));\r | |
123 | break;\r | |
124 | \r | |
125 | case CntpCtl:\r | |
126 | ArmWriteCntpCtl (*((UINTN *)SrcBuf));\r | |
127 | break;\r | |
128 | \r | |
129 | case CntvTval:\r | |
130 | ArmWriteCntvTval (*((UINTN *)SrcBuf));\r | |
131 | break;\r | |
132 | \r | |
133 | case CntvCtl:\r | |
134 | ArmWriteCntvCtl (*((UINTN *)SrcBuf));\r | |
135 | break;\r | |
136 | \r | |
137 | case CntvCt:\r | |
138 | DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));\r | |
139 | break;\r | |
140 | \r | |
141 | case CntpCval:\r | |
142 | ArmWriteCntpCval (*((UINT64 *)SrcBuf) );\r | |
143 | break;\r | |
144 | \r | |
145 | case CntvCval:\r | |
146 | ArmWriteCntvCval (*((UINT64 *)SrcBuf) );\r | |
147 | break;\r | |
148 | \r | |
149 | case CntvOff:\r | |
150 | ArmWriteCntvOff (*((UINT64 *)SrcBuf));\r | |
151 | break;\r | |
152 | \r | |
153 | case CnthCtl:\r | |
154 | case CnthpTval:\r | |
155 | case CnthpCtl:\r | |
156 | case CnthpCval:\r | |
157 | DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r | |
158 | break;\r | |
159 | \r | |
160 | default:\r | |
161 | DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r | |
162 | }\r | |
163 | } else {\r | |
164 | DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r | |
165 | ASSERT (0);\r | |
166 | }\r | |
167 | }\r |