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1e57a462 1/** @file\r
2*\r
992a1f83 3* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
1e57a462 4*\r
3402aac7
RC
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
1e57a462 12*\r
13**/\r
14\r
992a1f83 15#include <Uefi.h>\r
1e57a462 16#include <Chipset/ArmV7.h>\r
17#include <Library/BaseMemoryLib.h>\r
18#include <Library/MemoryAllocationLib.h>\r
19#include <Library/ArmLib.h>\r
20#include <Library/BaseLib.h>\r
21#include <Library/DebugLib.h>\r
22#include "ArmV7Lib.h"\r
23#include "ArmLibPrivate.h"\r
25402f5d 24#include <Library/ArmArchTimerLib.h>\r
1e57a462 25\r
26VOID\r
27EFIAPI\r
28ArmArchTimerReadReg (\r
29 IN ARM_ARCH_TIMER_REGS Reg,\r
30 OUT VOID *DstBuf\r
31 )\r
32{\r
33 // Check if the Generic/Architecture timer is implemented\r
34 if (ArmIsArchTimerImplemented ()) {\r
1e57a462 35 switch (Reg) {\r
1e57a462 36 case CntFrq:\r
37 *((UINTN *)DstBuf) = ArmReadCntFrq ();\r
992a1f83 38 return;\r
1e57a462 39\r
40 case CntPct:\r
41 *((UINT64 *)DstBuf) = ArmReadCntPct ();\r
992a1f83 42 return;\r
1e57a462 43\r
44 case CntkCtl:\r
45 *((UINTN *)DstBuf) = ArmReadCntkCtl();\r
992a1f83 46 return;\r
1e57a462 47\r
48 case CntpTval:\r
49 *((UINTN *)DstBuf) = ArmReadCntpTval ();\r
992a1f83 50 return;\r
1e57a462 51\r
52 case CntpCtl:\r
53 *((UINTN *)DstBuf) = ArmReadCntpCtl ();\r
992a1f83 54 return;\r
1e57a462 55\r
56 case CntvTval:\r
57 *((UINTN *)DstBuf) = ArmReadCntvTval ();\r
992a1f83 58 return;\r
1e57a462 59\r
60 case CntvCtl:\r
61 *((UINTN *)DstBuf) = ArmReadCntvCtl ();\r
992a1f83 62 return;\r
1e57a462 63\r
64 case CntvCt:\r
65 *((UINT64 *)DstBuf) = ArmReadCntvCt ();\r
992a1f83 66 return;\r
1e57a462 67\r
68 case CntpCval:\r
69 *((UINT64 *)DstBuf) = ArmReadCntpCval ();\r
992a1f83 70 return;\r
1e57a462 71\r
72 case CntvCval:\r
73 *((UINT64 *)DstBuf) = ArmReadCntvCval ();\r
992a1f83 74 return;\r
1e57a462 75\r
76 case CntvOff:\r
77 *((UINT64 *)DstBuf) = ArmReadCntvOff ();\r
992a1f83 78 return;\r
1e57a462 79\r
80 case CnthCtl:\r
81 case CnthpTval:\r
82 case CnthpCtl:\r
83 case CnthpCval:\r
992a1f83 84 DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
1e57a462 85 break;\r
86\r
87 default:\r
88 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
89 }\r
90 } else {\r
91 DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
92 ASSERT (0);\r
93 }\r
992a1f83
OM
94\r
95 *((UINT64 *)DstBuf) = 0;\r
1e57a462 96}\r
97\r
98VOID\r
99EFIAPI\r
100ArmArchTimerWriteReg (\r
101 IN ARM_ARCH_TIMER_REGS Reg,\r
102 IN VOID *SrcBuf\r
103 )\r
104{\r
105 // Check if the Generic/Architecture timer is implemented\r
106 if (ArmIsArchTimerImplemented ()) {\r
107\r
108 switch (Reg) {\r
109\r
110 case CntFrq:\r
111 ArmWriteCntFrq (*((UINTN *)SrcBuf));\r
112 break;\r
113\r
114 case CntPct:\r
115 DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));\r
116 break;\r
117\r
118 case CntkCtl:\r
119 ArmWriteCntkCtl (*((UINTN *)SrcBuf));\r
120 break;\r
121\r
122 case CntpTval:\r
123 ArmWriteCntpTval (*((UINTN *)SrcBuf));\r
124 break;\r
125\r
126 case CntpCtl:\r
127 ArmWriteCntpCtl (*((UINTN *)SrcBuf));\r
128 break;\r
129\r
130 case CntvTval:\r
131 ArmWriteCntvTval (*((UINTN *)SrcBuf));\r
132 break;\r
133\r
134 case CntvCtl:\r
135 ArmWriteCntvCtl (*((UINTN *)SrcBuf));\r
136 break;\r
137\r
138 case CntvCt:\r
139 DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));\r
140 break;\r
141\r
142 case CntpCval:\r
143 ArmWriteCntpCval (*((UINT64 *)SrcBuf) );\r
144 break;\r
145\r
146 case CntvCval:\r
147 ArmWriteCntvCval (*((UINT64 *)SrcBuf) );\r
148 break;\r
149\r
150 case CntvOff:\r
151 ArmWriteCntvOff (*((UINT64 *)SrcBuf));\r
152 break;\r
153\r
154 case CnthCtl:\r
155 case CnthpTval:\r
156 case CnthpCtl:\r
157 case CnthpCval:\r
158 DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));\r
159 break;\r
160\r
161 default:\r
162 DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));\r
163 }\r
164 } else {\r
165 DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));\r
166 ASSERT (0);\r
167 }\r
168}\r
169\r
170VOID\r
171EFIAPI\r
172ArmArchTimerEnableTimer (\r
173 VOID\r
174 )\r
175{\r
176 UINTN TimerCtrlReg;\r
177\r
178 ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
179 TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r
180 ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
181}\r
182\r
183VOID\r
184EFIAPI\r
185ArmArchTimerDisableTimer (\r
186 VOID\r
187 )\r
188{\r
189 UINTN TimerCtrlReg;\r
190\r
191 ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
192 TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r
193 ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);\r
194}\r
195\r
196VOID\r
197EFIAPI\r
198ArmArchTimerSetTimerFreq (\r
199 IN UINTN FreqInHz\r
200 )\r
201{\r
202 ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);\r
203}\r
204\r
205UINTN\r
206EFIAPI\r
207ArmArchTimerGetTimerFreq (\r
208 VOID\r
209 )\r
210{\r
992a1f83 211 UINTN ArchTimerFreq;\r
1e57a462 212 ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);\r
213 return ArchTimerFreq;\r
214}\r
215\r
216UINTN\r
217EFIAPI\r
218ArmArchTimerGetTimerVal (\r
219 VOID\r
220 )\r
221{\r
222 UINTN ArchTimerVal;\r
223 ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);\r
224 return ArchTimerVal;\r
225}\r
226\r
227\r
228VOID\r
229EFIAPI\r
230ArmArchTimerSetTimerVal (\r
231 IN UINTN Val\r
232 )\r
233{\r
234 ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);\r
235}\r
236\r
237UINT64\r
238EFIAPI\r
239ArmArchTimerGetSystemCount (\r
240 VOID\r
241 )\r
242{\r
243 UINT64 SystemCount;\r
244 ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);\r
245 return SystemCount;\r
246}\r
247\r
248UINTN\r
249EFIAPI\r
250ArmArchTimerGetTimerCtrlReg (\r
251 VOID\r
252 )\r
253{\r
254 UINTN Val;\r
255 ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);\r
256 return Val;\r
257}\r
258\r
259VOID\r
260EFIAPI\r
261ArmArchTimerSetTimerCtrlReg (\r
262 UINTN Val\r
263 )\r
264{\r
265 ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);\r
266}\r
267\r
268VOID\r
269EFIAPI\r
270ArmArchTimerSetCompareVal (\r
271 IN UINT64 Val\r
272 )\r
273{\r
274 ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);\r
275}\r