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1bfda055 | 1 | /** @file\r |
2 | * File managing the MMU for ARMv7 architecture\r | |
3 | *\r | |
ff1f27c0 | 4 | * Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r |
1bfda055 | 5 | *\r |
3402aac7 RC |
6 | * This program and the accompanying materials\r |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
1bfda055 | 13 | *\r |
14 | **/\r | |
15 | \r | |
3402aac7 | 16 | #include <Uefi.h>\r |
1bfda055 | 17 | #include <Chipset/ArmV7.h>\r |
18 | #include <Library/BaseMemoryLib.h>\r | |
19 | #include <Library/MemoryAllocationLib.h>\r | |
20 | #include <Library/ArmLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
2cf4b608 | 22 | #include <Library/DebugLib.h>\r |
1bfda055 | 23 | #include "ArmV7Lib.h"\r |
24 | #include "ArmLibPrivate.h"\r | |
25 | \r | |
6adbd5b4 OM |
26 | UINT32\r |
27 | ConvertSectionAttributesToPageAttributes (\r | |
28 | IN UINT32 SectionAttributes,\r | |
29 | IN BOOLEAN IsLargePage\r | |
30 | )\r | |
31 | {\r | |
32 | UINT32 PageAttributes;\r | |
33 | \r | |
34 | PageAttributes = 0;\r | |
35 | PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);\r | |
36 | PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);\r | |
37 | PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);\r | |
38 | PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);\r | |
39 | PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);\r | |
40 | \r | |
41 | return PageAttributes;\r | |
42 | }\r | |
43 | \r | |
46ff196f AB |
44 | STATIC\r |
45 | BOOLEAN\r | |
46 | PreferNonshareableMemory (\r | |
47 | VOID\r | |
48 | )\r | |
49 | {\r | |
50 | UINTN Mmfr;\r | |
51 | UINTN Val;\r | |
52 | \r | |
53 | if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {\r | |
54 | return TRUE;\r | |
55 | }\r | |
56 | \r | |
57 | //\r | |
58 | // Check whether the innermost level of shareability (the level we will use\r | |
59 | // by default to map normal memory) is implemented with hardware coherency\r | |
60 | // support. Otherwise, revert to mapping as non-shareable.\r | |
61 | //\r | |
62 | Mmfr = ArmReadIdMmfr0 ();\r | |
63 | switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {\r | |
64 | case ID_MMFR0_SHARELVL_ONE:\r | |
65 | // one level of shareability\r | |
66 | Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;\r | |
67 | break;\r | |
68 | case ID_MMFR0_SHARELVL_TWO:\r | |
69 | // two levels of shareability\r | |
70 | Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;\r | |
71 | break;\r | |
72 | default:\r | |
73 | // unexpected value -> shareable is the safe option\r | |
74 | ASSERT (FALSE);\r | |
75 | return FALSE;\r | |
76 | }\r | |
77 | return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;\r | |
78 | }\r | |
79 | \r | |
a3202839 | 80 | STATIC\r |
2cf4b608 | 81 | VOID\r |
82 | PopulateLevel2PageTable (\r | |
83 | IN UINT32 *SectionEntry,\r | |
84 | IN UINT32 PhysicalBase,\r | |
85 | IN UINT32 RemainLength,\r | |
86 | IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r | |
bd6b9799 | 87 | )\r |
88 | {\r | |
2cf4b608 | 89 | UINT32* PageEntry;\r |
90 | UINT32 Pages;\r | |
91 | UINT32 Index;\r | |
92 | UINT32 PageAttributes;\r | |
93 | UINT32 SectionDescriptor;\r | |
94 | UINT32 TranslationTable;\r | |
95 | UINT32 BaseSectionAddress;\r | |
96 | \r | |
97 | switch (Attributes) {\r | |
98 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r | |
7fffeef9 | 99 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r |
2cf4b608 | 100 | PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;\r |
101 | break;\r | |
102 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r | |
7fffeef9 | 103 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r |
2cf4b608 | 104 | PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;\r |
105 | break;\r | |
106 | case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r | |
7fffeef9 | 107 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r |
2cf4b608 | 108 | PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;\r |
109 | break;\r | |
110 | case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r | |
7fffeef9 | 111 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r |
2cf4b608 | 112 | PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r |
113 | break;\r | |
114 | default:\r | |
115 | PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;\r | |
116 | break;\r | |
117 | }\r | |
118 | \r | |
46ff196f | 119 | if (PreferNonshareableMemory ()) {\r |
65ceda91 AB |
120 | PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;\r |
121 | }\r | |
122 | \r | |
2cf4b608 | 123 | // Check if the Section Entry has already been populated. Otherwise attach a\r |
124 | // Level 2 Translation Table to it\r | |
125 | if (*SectionEntry != 0) {\r | |
126 | // The entry must be a page table. Otherwise it exists an overlapping in the memory map\r | |
127 | if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {\r | |
128 | TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;\r | |
129 | } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {\r | |
130 | // Case where a virtual memory map descriptor overlapped a section entry\r | |
131 | \r | |
132 | // Allocate a Level2 Page Table for this Section\r | |
133 | TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r | |
134 | TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r | |
135 | \r | |
136 | // Translate the Section Descriptor into Page Descriptor\r | |
6adbd5b4 | 137 | SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);\r |
2cf4b608 | 138 | \r |
139 | BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);\r | |
140 | \r | |
141 | // Populate the new Level2 Page Table for the section\r | |
142 | PageEntry = (UINT32*)TranslationTable;\r | |
143 | for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {\r | |
144 | PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;\r | |
145 | }\r | |
146 | \r | |
147 | // Overwrite the section entry to point to the new Level2 Translation Table\r | |
148 | *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r | |
149 | (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r | |
150 | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r | |
151 | } else {\r | |
152 | // We do not support the other section type (16MB Section)\r | |
153 | ASSERT(0);\r | |
154 | return;\r | |
155 | }\r | |
156 | } else {\r | |
157 | TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));\r | |
158 | TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r | |
159 | \r | |
160 | ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);\r | |
161 | \r | |
162 | *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |\r | |
163 | (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |\r | |
164 | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;\r | |
165 | }\r | |
166 | \r | |
167 | PageEntry = ((UINT32 *)(TranslationTable) + ((PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT));\r | |
168 | Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;\r | |
169 | \r | |
170 | for (Index = 0; Index < Pages; Index++) {\r | |
171 | *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;\r | |
172 | PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;\r | |
173 | }\r | |
174 | \r | |
175 | }\r | |
176 | \r | |
a3202839 | 177 | STATIC\r |
1bfda055 | 178 | VOID\r |
179 | FillTranslationTable (\r | |
180 | IN UINT32 *TranslationTable,\r | |
181 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r | |
182 | )\r | |
183 | {\r | |
2cf4b608 | 184 | UINT32 *SectionEntry;\r |
1bfda055 | 185 | UINT32 Attributes;\r |
55df704d | 186 | UINT32 PhysicalBase;\r |
2cde2696 | 187 | UINT64 RemainLength;\r |
3402aac7 | 188 | \r |
2cf4b608 | 189 | ASSERT(MemoryRegion->Length > 0);\r |
190 | \r | |
55df704d AB |
191 | if (MemoryRegion->PhysicalBase >= SIZE_4GB) {\r |
192 | return;\r | |
193 | }\r | |
194 | \r | |
195 | PhysicalBase = MemoryRegion->PhysicalBase;\r | |
196 | RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);\r | |
197 | \r | |
1bfda055 | 198 | switch (MemoryRegion->Attributes) {\r |
199 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r | |
200 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r | |
201 | break;\r | |
202 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r | |
203 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r | |
204 | break;\r | |
205 | case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r | |
206 | Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);\r | |
207 | break;\r | |
208 | case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r | |
209 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r | |
210 | break;\r | |
7fffeef9 | 211 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r |
1bfda055 | 212 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r |
213 | break;\r | |
7fffeef9 | 214 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r |
1bfda055 | 215 | Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r |
216 | break;\r | |
7fffeef9 | 217 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r |
1bfda055 | 218 | Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);\r |
219 | break;\r | |
7fffeef9 | 220 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r |
1bfda055 | 221 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r |
222 | break;\r | |
223 | default:\r | |
224 | Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r | |
225 | break;\r | |
226 | }\r | |
3402aac7 | 227 | \r |
46ff196f | 228 | if (PreferNonshareableMemory ()) {\r |
65ceda91 AB |
229 | Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;\r |
230 | }\r | |
231 | \r | |
2cf4b608 | 232 | // Get the first section entry for this mapping\r |
233 | SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r | |
234 | \r | |
235 | while (RemainLength != 0) {\r | |
236 | if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) {\r | |
237 | if (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {\r | |
238 | // Case: Physical address aligned on the Section Size (1MB) && the length is greater than the Section Size\r | |
239 | *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r | |
240 | PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r | |
241 | } else {\r | |
242 | // Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section\r | |
bd6b9799 | 243 | PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r |
2cf4b608 | 244 | \r |
245 | // It must be the last entry\r | |
246 | break;\r | |
247 | }\r | |
248 | } else {\r | |
249 | // Case: Physical address NOT aligned on the Section Size (1MB)\r | |
bd6b9799 | 250 | PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);\r |
2cf4b608 | 251 | // Aligned the address\r |
252 | PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);\r | |
253 | \r | |
254 | // If it is the last entry\r | |
255 | if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {\r | |
256 | break;\r | |
257 | }\r | |
258 | }\r | |
259 | RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;\r | |
1bfda055 | 260 | }\r |
261 | }\r | |
262 | \r | |
6f050ad6 | 263 | RETURN_STATUS\r |
1bfda055 | 264 | EFIAPI\r |
265 | ArmConfigureMmu (\r | |
266 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r | |
6f050ad6 OM |
267 | OUT VOID **TranslationTableBase OPTIONAL,\r |
268 | OUT UINTN *TranslationTableSize OPTIONAL\r | |
1bfda055 | 269 | )\r |
270 | {\r | |
6f050ad6 | 271 | VOID* TranslationTable;\r |
1bfda055 | 272 | ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute;\r |
273 | UINT32 TTBRAttributes;\r | |
274 | \r | |
275 | // Allocate pages for translation table.\r | |
6f050ad6 OM |
276 | TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));\r |
277 | if (TranslationTable == NULL) {\r | |
278 | return RETURN_OUT_OF_RESOURCES;\r | |
279 | }\r | |
280 | TranslationTable = (VOID*)(((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK);\r | |
1bfda055 | 281 | \r |
282 | if (TranslationTableBase != NULL) {\r | |
6f050ad6 | 283 | *TranslationTableBase = TranslationTable;\r |
1bfda055 | 284 | }\r |
3402aac7 | 285 | \r |
526099f9 | 286 | if (TranslationTableSize != NULL) {\r |
1bfda055 | 287 | *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;\r |
288 | }\r | |
289 | \r | |
6f050ad6 | 290 | ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r |
1bfda055 | 291 | \r |
6f050ad6 OM |
292 | // By default, mark the translation table as belonging to a uncached region\r |
293 | TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r | |
1bfda055 | 294 | while (MemoryTable->Length != 0) {\r |
295 | // Find the memory attribute for the Translation Table\r | |
6f050ad6 | 296 | if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {\r |
1bfda055 | 297 | TranslationTableAttribute = MemoryTable->Attributes;\r |
298 | }\r | |
299 | \r | |
6f050ad6 | 300 | FillTranslationTable (TranslationTable, MemoryTable);\r |
1bfda055 | 301 | MemoryTable++;\r |
302 | }\r | |
303 | \r | |
304 | // Translate the Memory Attributes into Translation Table Register Attributes\r | |
3402aac7 | 305 | if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||\r |
7fffeef9 | 306 | (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r |
72143137 | 307 | TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE;\r |
3402aac7 | 308 | } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r |
7fffeef9 | 309 | (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r |
72143137 | 310 | TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;\r |
3402aac7 | 311 | } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||\r |
7fffeef9 | 312 | (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r |
72143137 | 313 | TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH;\r |
1bfda055 | 314 | } else {\r |
6f050ad6 OM |
315 | ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to.\r |
316 | return RETURN_UNSUPPORTED;\r | |
1bfda055 | 317 | }\r |
318 | \r | |
07070ecc | 319 | if (TTBRAttributes & TTBR_SHAREABLE) {\r |
46ff196f | 320 | if (PreferNonshareableMemory ()) {\r |
65ceda91 AB |
321 | TTBRAttributes ^= TTBR_SHAREABLE;\r |
322 | } else {\r | |
323 | //\r | |
324 | // Unlike the S bit in the short descriptors, which implies inner shareable\r | |
325 | // on an implementation that supports two levels, the meaning of the S bit\r | |
326 | // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.\r | |
327 | // However, we should only set this bit after we have confirmed that the\r | |
328 | // implementation supports multiple levels, or else the NOS bit is UNK/SBZP\r | |
329 | //\r | |
330 | if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {\r | |
331 | TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;\r | |
332 | }\r | |
07070ecc AB |
333 | }\r |
334 | }\r | |
335 | \r | |
ffb91edf EC |
336 | ArmCleanInvalidateDataCache ();\r |
337 | ArmInvalidateInstructionCache ();\r | |
338 | \r | |
339 | ArmDisableDataCache ();\r | |
340 | ArmDisableInstructionCache();\r | |
341 | // TLBs are also invalidated when calling ArmDisableMmu()\r | |
342 | ArmDisableMmu ();\r | |
343 | \r | |
344 | // Make sure nothing sneaked into the cache\r | |
345 | ArmCleanInvalidateDataCache ();\r | |
346 | ArmInvalidateInstructionCache ();\r | |
347 | \r | |
6f050ad6 | 348 | ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));\r |
3402aac7 | 349 | \r |
ff1f27c0 EL |
350 | //\r |
351 | // The TTBCR register value is undefined at reset in the Non-Secure world.\r | |
352 | // Writing 0 has the effect of:\r | |
353 | // Clearing EAE: Use short descriptors, as mandated by specification.\r | |
354 | // Clearing PD0 and PD1: Translation Table Walk Disable is off.\r | |
355 | // Clearing N: Perform all translation table walks through TTBR0.\r | |
356 | // (0 is the default reset value in systems not implementing\r | |
357 | // the Security Extensions.)\r | |
358 | //\r | |
359 | ArmSetTTBCR (0);\r | |
360 | \r | |
1bfda055 | 361 | ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r |
362 | DOMAIN_ACCESS_CONTROL_NONE(14) |\r | |
363 | DOMAIN_ACCESS_CONTROL_NONE(13) |\r | |
364 | DOMAIN_ACCESS_CONTROL_NONE(12) |\r | |
365 | DOMAIN_ACCESS_CONTROL_NONE(11) |\r | |
366 | DOMAIN_ACCESS_CONTROL_NONE(10) |\r | |
367 | DOMAIN_ACCESS_CONTROL_NONE( 9) |\r | |
368 | DOMAIN_ACCESS_CONTROL_NONE( 8) |\r | |
369 | DOMAIN_ACCESS_CONTROL_NONE( 7) |\r | |
370 | DOMAIN_ACCESS_CONTROL_NONE( 6) |\r | |
371 | DOMAIN_ACCESS_CONTROL_NONE( 5) |\r | |
372 | DOMAIN_ACCESS_CONTROL_NONE( 4) |\r | |
373 | DOMAIN_ACCESS_CONTROL_NONE( 3) |\r | |
374 | DOMAIN_ACCESS_CONTROL_NONE( 2) |\r | |
375 | DOMAIN_ACCESS_CONTROL_NONE( 1) |\r | |
6bc35cba | 376 | DOMAIN_ACCESS_CONTROL_CLIENT(0));\r |
3402aac7 | 377 | \r |
1bfda055 | 378 | ArmEnableInstructionCache();\r |
379 | ArmEnableDataCache();\r | |
380 | ArmEnableMmu();\r | |
6f050ad6 | 381 | return RETURN_SUCCESS;\r |
1bfda055 | 382 | }\r |
4d9a4f62 AB |
383 | \r |
384 | RETURN_STATUS\r | |
385 | ArmSetMemoryRegionNoExec (\r | |
386 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
387 | IN UINT64 Length\r | |
388 | )\r | |
389 | {\r | |
390 | return RETURN_UNSUPPORTED;\r | |
391 | }\r | |
392 | \r | |
393 | RETURN_STATUS\r | |
394 | ArmClearMemoryRegionNoExec (\r | |
395 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
396 | IN UINT64 Length\r | |
397 | )\r | |
398 | {\r | |
399 | return RETURN_UNSUPPORTED;\r | |
400 | }\r | |
401 | \r | |
402 | RETURN_STATUS\r | |
403 | ArmSetMemoryRegionReadOnly (\r | |
404 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
405 | IN UINT64 Length\r | |
406 | )\r | |
407 | {\r | |
408 | return RETURN_UNSUPPORTED;\r | |
409 | }\r | |
410 | \r | |
411 | RETURN_STATUS\r | |
412 | ArmClearMemoryRegionReadOnly (\r | |
413 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
414 | IN UINT64 Length\r | |
415 | )\r | |
416 | {\r | |
417 | return RETURN_UNSUPPORTED;\r | |
418 | }\r |