[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.S

#------------------------------------------------------------------------------ 
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution.  The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------

.globl ASM_PFX(ArmInvalidateInstructionCache)
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
.globl ASM_PFX(ArmDrainWriteBuffer)
.globl ASM_PFX(ArmEnableMmu)
.globl ASM_PFX(ArmDisableMmu)
.globl ASM_PFX(ArmMmuEnabled)
.globl ASM_PFX(ArmEnableDataCache)
.globl ASM_PFX(ArmDisableDataCache)
.globl ASM_PFX(ArmEnableInstructionCache)
.globl ASM_PFX(ArmDisableInstructionCache)
.globl ASM_PFX(ArmEnableBranchPrediction)
.globl ASM_PFX(ArmDisableBranchPrediction)
.globl ASM_PFX(ArmV7AllDataCachesOperation)
.globl ASM_PFX(ArmDataMemoryBarrier)
.globl ASM_PFX(ArmDataSyncronizationBarrier) 
.globl ASM_PFX(ArmInstructionSynchronizationBarrier)

.text
.align 2

.set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12)


ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line       
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  dsb
  isb
  bx      lr


ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line		
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line		
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line		
  dsb
  isb
  bx      lr


ASM_PFX(ArmInvalidateInstructionCache):
  mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableMmu):
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  dsb
  isb
  bx      LR

ASM_PFX(ArmMmuEnabled):
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  bx      LR

ASM_PFX(ArmDisableMmu):
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0      @Disable MMU

	mcr 		p15,0,R0,c8,c7,0      @Invalidate TLB
  mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableDataCache):
  ldr     R1,=DC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  orr     R0,R0,R1              @Set C bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR
    
ASM_PFX(ArmDisableDataCache):
  ldr     R1,=DC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  bic     R0,R0,R1              @Clear C bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableInstructionCache):
  ldr     R1,=IC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  orr     R0,R0,R1              @Set I bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR
  
ASM_PFX(ArmDisableInstructionCache):
  ldr     R1,=IC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  bic     R0,R0,R1              @Clear I bit.
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableBranchPrediction):
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  dsb
  isb
  bx      LR

ASM_PFX(ArmDisableBranchPrediction):
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  dsb
  isb
  bx      LR


ASM_PFX(ArmV7AllDataCachesOperation):
  stmfd SP!,{r4-r12, LR}
  mov   R1, R0                @ Save Function call in R1
  mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
  ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
  mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
  beq   L_Finished
  mov   R10, #0

Loop1:   
  add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
  mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
  and   R12, R12, #7          @ get those 3 bits alone
  cmp   R12, #2
  blt   L_Skip                  @ no cache or only instruction cache at this level
  mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
  isb                           @ isb to sync the change to the CacheSizeID reg 
  mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
  and   R2, R12, #0x7           @ extract the line length field
  add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
@  ldr   R4, =0x3FF
  mov   R4, #0x400
  sub   R4, R4, #1
  ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
  clz   R5, R4                  @ R5 is the bit position of the way size increment
@  ldr   R7, =0x00007FFF
  mov   R7, #0x00008000
  sub   R7, R7, #1
  ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)

Loop2:   
  mov   R9, R4                  @ R9 working copy of the max way size (right aligned)

Loop3:   
  orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
  orr   R0, R0, R7, LSL R2      @ factor in the index number

  blx   R1

  subs  R9, R9, #1              @ decrement the way number
  bge   Loop3
  subs  R7, R7, #1              @ decrement the index
  bge   Loop2
L_Skip:  
  add   R10, R10, #2            @ increment the cache number
  cmp   R3, R10
  bgt   Loop1
  
L_Finished:
  dsb
  ldmfd SP!, {r4-r12, lr}
  bx    LR

ASM_PFX(ArmDataMemoryBarrier):
  dmb
  bx      LR
  
ASM_PFX(ArmDataSyncronizationBarrier):
ASM_PFX(ArmDrainWriteBuffer):
  dsb
  bx      LR
  
ASM_PFX(ArmInstructionSynchronizationBarrier):
  isb
  bx      LR
 

ASM_FUNCTION_REMOVE_IF_UNREFERENCED
Commit	Line	Data
2ef2b01e A	1	#------------------------------------------------------------------------------
	2	#
	3	# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	#
	5	# All rights reserved. This program and the accompanying materials
	6	# are licensed and made available under the terms and conditions of the BSD License
	7	# which accompanies this distribution. The full text of the license may be found at
	8	# http://opensource.org/licenses/bsd-license.php
	9	#
	10	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	#
	13	#------------------------------------------------------------------------------
	14
2ef2b01e A	15	.globl ASM_PFX(ArmInvalidateInstructionCache)
	16	.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
	17	.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
	18	.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
	19	.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
	20	.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
	21	.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
	22	.globl ASM_PFX(ArmDrainWriteBuffer)
	23	.globl ASM_PFX(ArmEnableMmu)
	24	.globl ASM_PFX(ArmDisableMmu)
c2b5ca8b	25	.globl ASM_PFX(ArmMmuEnabled)
2ef2b01e A	26	.globl ASM_PFX(ArmEnableDataCache)
	27	.globl ASM_PFX(ArmDisableDataCache)
	28	.globl ASM_PFX(ArmEnableInstructionCache)
	29	.globl ASM_PFX(ArmDisableInstructionCache)
2ef2b01e A	30	.globl ASM_PFX(ArmEnableBranchPrediction)
2ef2b01e A	31	.globl ASM_PFX(ArmDisableBranchPrediction)
98bc0c8c	32	.globl ASM_PFX(ArmV7AllDataCachesOperation)
026c3d34	33	.globl ASM_PFX(ArmDataMemoryBarrier)
	34	.globl ASM_PFX(ArmDataSyncronizationBarrier)
	35	.globl ASM_PFX(ArmInstructionSynchronizationBarrier)
	36
548af3e7	37	.text
548af3e7	38	.align 2
2ef2b01e A	39
	40	.set DC_ON, (0x1<<2)
	41	.set IC_ON, (0x1<<12)
98bc0c8c	42
2ef2b01e	43
7800c283	44
2ef2b01e	45	ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
98bc0c8c	46	mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
	47	dsb
	48	isb
2ef2b01e A	49	bx lr
	50
	51
	52	ASM_PFX(ArmCleanDataCacheEntryByMVA):
	53	mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
98bc0c8c	54	dsb
98bc0c8c	55	isb
2ef2b01e A	56	bx lr
	57
	58
	59	ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
	60	mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
98bc0c8c	61	dsb
98bc0c8c	62	isb
2ef2b01e A	63	bx lr
	64
	65
	66	ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
	67	mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
98bc0c8c	68	dsb
98bc0c8c	69	isb
2ef2b01e A	70	bx lr
	71
	72
	73	ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
	74	mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
98bc0c8c	75	dsb
98bc0c8c	76	isb
2ef2b01e A	77	bx lr
	78
	79
	80	ASM_PFX(ArmCleanDataCacheEntryBySetWay):
	81	mcr p15, 0, r0, c7, c10, 2 @ Clean this line
98bc0c8c	82	dsb
98bc0c8c	83	isb
2ef2b01e A	84	bx lr
	85
	86
2ef2b01e	87	ASM_PFX(ArmInvalidateInstructionCache):
2ef2b01e	88	mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
98bc0c8c	89	dsb
98bc0c8c	90	isb
2ef2b01e A	91	bx LR
	92
	93	ASM_PFX(ArmEnableMmu):
	94	mrc p15,0,R0,c1,c0,0
	95	orr R0,R0,#1
	96	mcr p15,0,R0,c1,c0,0
548af3e7	97	dsb
548af3e7	98	isb
2ef2b01e A	99	bx LR
2ef2b01e A	100
c2b5ca8b A	101	ASM_PFX(ArmMmuEnabled):
	102	mrc p15,0,R0,c1,c0,0
	103	and R0,R0,#1
	104	bx LR
	105
2ef2b01e	106	ASM_PFX(ArmDisableMmu):
2ef2b01e A	107	mrc p15,0,R0,c1,c0,0
	108	bic R0,R0,#1
	109	mcr p15,0,R0,c1,c0,0 @Disable MMU
7800c283	110
	111	mcr p15,0,R0,c8,c7,0 @Invalidate TLB
	112	mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
98bc0c8c	113	dsb
98bc0c8c	114	isb
2ef2b01e A	115	bx LR
	116
	117	ASM_PFX(ArmEnableDataCache):
	118	ldr R1,=DC_ON
	119	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	120	orr R0,R0,R1 @Set C bit
	121	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	122	dsb
98bc0c8c	123	isb
2ef2b01e A	124	bx LR
	125
	126	ASM_PFX(ArmDisableDataCache):
	127	ldr R1,=DC_ON
	128	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	129	bic R0,R0,R1 @Clear C bit
	130	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	131	dsb
98bc0c8c	132	isb
2ef2b01e A	133	bx LR
	134
	135	ASM_PFX(ArmEnableInstructionCache):
	136	ldr R1,=IC_ON
	137	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	138	orr R0,R0,R1 @Set I bit
	139	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	140	dsb
98bc0c8c	141	isb
2ef2b01e A	142	bx LR
	143
	144	ASM_PFX(ArmDisableInstructionCache):
	145	ldr R1,=IC_ON
	146	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	147	bic R0,R0,R1 @Clear I bit.
	148	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	149	dsb
98bc0c8c	150	isb
2ef2b01e A	151	bx LR
	152
	153	ASM_PFX(ArmEnableBranchPrediction):
	154	mrc p15, 0, r0, c1, c0, 0
	155	orr r0, r0, #0x00000800
	156	mcr p15, 0, r0, c1, c0, 0
98bc0c8c	157	dsb
98bc0c8c	158	isb
2ef2b01e A	159	bx LR
	160
	161	ASM_PFX(ArmDisableBranchPrediction):
	162	mrc p15, 0, r0, c1, c0, 0
	163	bic r0, r0, #0x00000800
	164	mcr p15, 0, r0, c1, c0, 0
98bc0c8c	165	dsb
98bc0c8c	166	isb
2ef2b01e A	167	bx LR
2ef2b01e A	168
98bc0c8c	169
	170	ASM_PFX(ArmV7AllDataCachesOperation):
	171	stmfd SP!,{r4-r12, LR}
	172	mov R1, R0 @ Save Function call in R1
	173	mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
	174	ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
	175	mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
	176	beq L_Finished
	177	mov R10, #0
	178
	179	Loop1:
	180	add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
	181	mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
	182	and R12, R12, #7 @ get those 3 bits alone
	183	cmp R12, #2
	184	blt L_Skip @ no cache or only instruction cache at this level
	185	mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
548af3e7	186	isb @ isb to sync the change to the CacheSizeID reg
548af3e7	187	mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
98bc0c8c	188	and R2, R12, #0x7 @ extract the line length field
548af3e7	189	add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
548af3e7	190	@ ldr R4, =0x3FF
98bc0c8c	191	mov R4, #0x400
	192	sub R4, R4, #1
	193	ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
	194	clz R5, R4 @ R5 is the bit position of the way size increment
548af3e7	195	@ ldr R7, =0x00007FFF
98bc0c8c	196	mov R7, #0x00008000
	197	sub R7, R7, #1
	198	ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
	199
	200	Loop2:
	201	mov R9, R4 @ R9 working copy of the max way size (right aligned)
	202
	203	Loop3:
	204	orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
	205	orr R0, R0, R7, LSL R2 @ factor in the index number
	206
	207	blx R1
	208
	209	subs R9, R9, #1 @ decrement the way number
	210	bge Loop3
	211	subs R7, R7, #1 @ decrement the index
	212	bge Loop2
	213	L_Skip:
	214	add R10, R10, #2 @ increment the cache number
	215	cmp R3, R10
	216	bgt Loop1
	217
	218	L_Finished:
7800c283	219	dsb
98bc0c8c	220	ldmfd SP!, {r4-r12, lr}
	221	bx LR
	222
026c3d34	223	ASM_PFX(ArmDataMemoryBarrier):
	224	dmb
	225	bx LR
	226
	227	ASM_PFX(ArmDataSyncronizationBarrier):
7800c283	228	ASM_PFX(ArmDrainWriteBuffer):
026c3d34	229	dsb
	230	bx LR
	231
	232	ASM_PFX(ArmInstructionSynchronizationBarrier):
	233	isb
	234	bx LR
	235
98bc0c8c	236
2ef2b01e	237	ASM_FUNCTION_REMOVE_IF_UNREFERENCED