[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.S

#------------------------------------------------------------------------------ 
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution.  The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------

.text
.align 2
.globl ASM_PFX(ArmInvalidateInstructionCache)
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
.globl ASM_PFX(ArmDrainWriteBuffer)
.globl ASM_PFX(ArmEnableMmu)
.globl ASM_PFX(ArmDisableMmu)
.globl ASM_PFX(ArmMmuEnabled)
.globl ASM_PFX(ArmEnableDataCache)
.globl ASM_PFX(ArmDisableDataCache)
.globl ASM_PFX(ArmEnableInstructionCache)
.globl ASM_PFX(ArmDisableInstructionCache)
.globl ASM_PFX(ArmEnableExtendPTConfig)
.globl ASM_PFX(ArmDisableExtendPTConfig)
.globl ASM_PFX(ArmEnableBranchPrediction)
.globl ASM_PFX(ArmDisableBranchPrediction)
.globl ASM_PFX(ArmV7AllDataCachesOperation)

.set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12)


ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line       
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  dsb
  isb
  bx      lr


ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line		
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line		
  dsb
  isb
  bx      lr


ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line		
  dsb
  isb
  bx      lr


ASM_PFX(ArmDrainWriteBuffer):
  mcr     p15, 0, r0, c7, c10, 4       @ Drain write buffer for sync
  dsb
  isb
  bx      lr
  

ASM_PFX(ArmInvalidateInstructionCache):
  mov     R0,#0
  mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  mov     R0,#0
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableMmu):
  mrc     p15,0,R0,c1,c0,0
  orr     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0
  bx      LR

ASM_PFX(ArmMmuEnabled):
  mrc     p15,0,R0,c1,c0,0
  and     R0,R0,#1
  bx      LR


ASM_PFX(ArmDisableMmu):
  mov     R0,#0
  mcr     p15,0,R0,c13,c0,0     @FCSE PID register must be cleared before disabling MMU
  mrc     p15,0,R0,c1,c0,0
  bic     R0,R0,#1
  mcr     p15,0,R0,c1,c0,0      @Disable MMU
  mov     R0,#0
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableDataCache):
  ldr     R1,=DC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  orr     R0,R0,R1              @Set C bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR
    
ASM_PFX(ArmDisableDataCache):
  ldr     R1,=DC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  bic     R0,R0,R1              @Clear C bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableInstructionCache):
  ldr     R1,=IC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  orr     R0,R0,R1              @Set I bit
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR
  
ASM_PFX(ArmDisableInstructionCache):
  ldr     R1,=IC_ON
  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  bic     R0,R0,R1              @Clear I bit.
  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  dsb
  isb
  bx      LR

ASM_PFX(ArmEnableBranchPrediction):
  mrc     p15, 0, r0, c1, c0, 0
  orr     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  dsb
  isb
  bx      LR

ASM_PFX(ArmDisableBranchPrediction):
  mrc     p15, 0, r0, c1, c0, 0
  bic     r0, r0, #0x00000800
  mcr     p15, 0, r0, c1, c0, 0
  dsb
  isb
  bx      LR


ASM_PFX(ArmV7AllDataCachesOperation):
  stmfd SP!,{r4-r12, LR}
  mov   R1, R0                @ Save Function call in R1
  mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
  ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
  mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
  beq   L_Finished
  mov   R10, #0

Loop1:   
  add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
  mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
  and   R12, R12, #7          @ get those 3 bits alone
  cmp   R12, #2
  blt   L_Skip                  @ no cache or only instruction cache at this level
  mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
  isb                           @ ISB to sync the change to the CacheSizeID reg 
  mcr   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
  and   R2, R12, #0x7           @ extract the line length field
  and   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
  mov   R4, #0x400
  sub   R4, R4, #1
  ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
  clz   R5, R4                  @ R5 is the bit position of the way size increment
  mov   R7, #0x00008000
  sub   R7, R7, #1
  ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)

Loop2:   
  mov   R9, R4                  @ R9 working copy of the max way size (right aligned)

Loop3:   
  orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
  orr   R0, R0, R7, LSL R2      @ factor in the index number

  blx   R1

  subs  R9, R9, #1              @ decrement the way number
  bge   Loop3
  subs  R7, R7, #1              @ decrement the index
  bge   Loop2
L_Skip:  
  add   R10, R10, #2            @ increment the cache number
  cmp   R3, R10
  bgt   Loop1
  
L_Finished:
  ldmfd SP!, {r4-r12, lr}
  bx    LR


ASM_FUNCTION_REMOVE_IF_UNREFERENCED
Commit	Line	Data
2ef2b01e A	1	#------------------------------------------------------------------------------
	2	#
	3	# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
	4	#
	5	# All rights reserved. This program and the accompanying materials
	6	# are licensed and made available under the terms and conditions of the BSD License
	7	# which accompanies this distribution. The full text of the license may be found at
	8	# http://opensource.org/licenses/bsd-license.php
	9	#
	10	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
	11	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
	12	#
	13	#------------------------------------------------------------------------------
	14
	15	.text
	16	.align 2
	17	.globl ASM_PFX(ArmInvalidateInstructionCache)
	18	.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
	19	.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
	20	.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
	21	.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
	22	.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
	23	.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
	24	.globl ASM_PFX(ArmDrainWriteBuffer)
	25	.globl ASM_PFX(ArmEnableMmu)
	26	.globl ASM_PFX(ArmDisableMmu)
c2b5ca8b	27	.globl ASM_PFX(ArmMmuEnabled)
2ef2b01e A	28	.globl ASM_PFX(ArmEnableDataCache)
	29	.globl ASM_PFX(ArmDisableDataCache)
	30	.globl ASM_PFX(ArmEnableInstructionCache)
	31	.globl ASM_PFX(ArmDisableInstructionCache)
	32	.globl ASM_PFX(ArmEnableExtendPTConfig)
	33	.globl ASM_PFX(ArmDisableExtendPTConfig)
	34	.globl ASM_PFX(ArmEnableBranchPrediction)
	35	.globl ASM_PFX(ArmDisableBranchPrediction)
98bc0c8c	36	.globl ASM_PFX(ArmV7AllDataCachesOperation)
2ef2b01e A	37
	38	.set DC_ON, (0x1<<2)
	39	.set IC_ON, (0x1<<12)
98bc0c8c	40
2ef2b01e A	41
2ef2b01e A	42	ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
98bc0c8c	43	mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
	44	dsb
	45	isb
2ef2b01e A	46	bx lr
	47
	48
	49	ASM_PFX(ArmCleanDataCacheEntryByMVA):
	50	mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
98bc0c8c	51	dsb
98bc0c8c	52	isb
2ef2b01e A	53	bx lr
	54
	55
	56	ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
	57	mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
98bc0c8c	58	dsb
98bc0c8c	59	isb
2ef2b01e A	60	bx lr
	61
	62
	63	ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
	64	mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
98bc0c8c	65	dsb
98bc0c8c	66	isb
2ef2b01e A	67	bx lr
	68
	69
	70	ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
	71	mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
98bc0c8c	72	dsb
98bc0c8c	73	isb
2ef2b01e A	74	bx lr
	75
	76
	77	ASM_PFX(ArmCleanDataCacheEntryBySetWay):
	78	mcr p15, 0, r0, c7, c10, 2 @ Clean this line
98bc0c8c	79	dsb
98bc0c8c	80	isb
2ef2b01e A	81	bx lr
	82
	83
	84	ASM_PFX(ArmDrainWriteBuffer):
	85	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer for sync
98bc0c8c	86	dsb
98bc0c8c	87	isb
2ef2b01e A	88	bx lr
	89
	90
	91	ASM_PFX(ArmInvalidateInstructionCache):
	92	mov R0,#0
	93	mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
	94	mov R0,#0
98bc0c8c	95	dsb
98bc0c8c	96	isb
2ef2b01e A	97	bx LR
	98
	99	ASM_PFX(ArmEnableMmu):
	100	mrc p15,0,R0,c1,c0,0
	101	orr R0,R0,#1
	102	mcr p15,0,R0,c1,c0,0
	103	bx LR
	104
c2b5ca8b A	105	ASM_PFX(ArmMmuEnabled):
	106	mrc p15,0,R0,c1,c0,0
	107	and R0,R0,#1
	108	bx LR
	109
	110
2ef2b01e A	111	ASM_PFX(ArmDisableMmu):
	112	mov R0,#0
	113	mcr p15,0,R0,c13,c0,0 @FCSE PID register must be cleared before disabling MMU
	114	mrc p15,0,R0,c1,c0,0
	115	bic R0,R0,#1
	116	mcr p15,0,R0,c1,c0,0 @Disable MMU
	117	mov R0,#0
98bc0c8c	118	dsb
98bc0c8c	119	isb
2ef2b01e A	120	bx LR
	121
	122	ASM_PFX(ArmEnableDataCache):
	123	ldr R1,=DC_ON
	124	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	125	orr R0,R0,R1 @Set C bit
	126	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	127	dsb
98bc0c8c	128	isb
2ef2b01e A	129	bx LR
	130
	131	ASM_PFX(ArmDisableDataCache):
	132	ldr R1,=DC_ON
	133	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	134	bic R0,R0,R1 @Clear C bit
	135	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	136	dsb
98bc0c8c	137	isb
2ef2b01e A	138	bx LR
	139
	140	ASM_PFX(ArmEnableInstructionCache):
	141	ldr R1,=IC_ON
	142	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	143	orr R0,R0,R1 @Set I bit
	144	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	145	dsb
98bc0c8c	146	isb
2ef2b01e A	147	bx LR
	148
	149	ASM_PFX(ArmDisableInstructionCache):
	150	ldr R1,=IC_ON
	151	mrc p15,0,R0,c1,c0,0 @Read control register configuration data
	152	bic R0,R0,R1 @Clear I bit.
	153	mcr p15,0,r0,c1,c0,0 @Write control register configuration data
98bc0c8c	154	dsb
98bc0c8c	155	isb
2ef2b01e A	156	bx LR
	157
	158	ASM_PFX(ArmEnableBranchPrediction):
	159	mrc p15, 0, r0, c1, c0, 0
	160	orr r0, r0, #0x00000800
	161	mcr p15, 0, r0, c1, c0, 0
98bc0c8c	162	dsb
98bc0c8c	163	isb
2ef2b01e A	164	bx LR
	165
	166	ASM_PFX(ArmDisableBranchPrediction):
	167	mrc p15, 0, r0, c1, c0, 0
	168	bic r0, r0, #0x00000800
	169	mcr p15, 0, r0, c1, c0, 0
98bc0c8c	170	dsb
98bc0c8c	171	isb
2ef2b01e A	172	bx LR
2ef2b01e A	173
98bc0c8c	174
	175	ASM_PFX(ArmV7AllDataCachesOperation):
	176	stmfd SP!,{r4-r12, LR}
	177	mov R1, R0 @ Save Function call in R1
	178	mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
	179	ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
	180	mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
	181	beq L_Finished
	182	mov R10, #0
	183
	184	Loop1:
	185	add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
	186	mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
	187	and R12, R12, #7 @ get those 3 bits alone
	188	cmp R12, #2
	189	blt L_Skip @ no cache or only instruction cache at this level
	190	mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
	191	isb @ ISB to sync the change to the CacheSizeID reg
	192	mcr p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
	193	and R2, R12, #0x7 @ extract the line length field
	194	and R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
	195	mov R4, #0x400
	196	sub R4, R4, #1
	197	ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
	198	clz R5, R4 @ R5 is the bit position of the way size increment
	199	mov R7, #0x00008000
	200	sub R7, R7, #1
	201	ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
	202
	203	Loop2:
	204	mov R9, R4 @ R9 working copy of the max way size (right aligned)
	205
	206	Loop3:
	207	orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
	208	orr R0, R0, R7, LSL R2 @ factor in the index number
	209
	210	blx R1
	211
	212	subs R9, R9, #1 @ decrement the way number
	213	bge Loop3
	214	subs R7, R7, #1 @ decrement the index
	215	bge Loop2
	216	L_Skip:
	217	add R10, R10, #2 @ increment the cache number
	218	cmp R3, R10
	219	bgt Loop1
	220
	221	L_Finished:
	222	ldmfd SP!, {r4-r12, lr}
	223	bx LR
	224
	225
2ef2b01e	226	ASM_FUNCTION_REMOVE_IF_UNREFERENCED