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3402aac7 | 1 | #------------------------------------------------------------------------------\r |
bd6b9799 | 2 | #\r |
3 | # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
9401d6f4 | 4 | # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | #\r |
6 | # This program and the accompanying materials\r | |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | #\r | |
14 | #------------------------------------------------------------------------------\r | |
15 | \r | |
16 | .text\r | |
17 | .align 2\r | |
18 | \r | |
19 | GCC_ASM_EXPORT (ArmInvalidateInstructionCache)\r | |
20 | GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)\r | |
21 | GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)\r | |
b7de7e3c | 22 | GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)\r |
bd6b9799 | 23 | GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)\r |
24 | GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)\r | |
25 | GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)\r | |
26 | GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)\r | |
bd6b9799 | 27 | GCC_ASM_EXPORT (ArmEnableMmu)\r |
28 | GCC_ASM_EXPORT (ArmDisableMmu)\r | |
29 | GCC_ASM_EXPORT (ArmDisableCachesAndMmu)\r | |
30 | GCC_ASM_EXPORT (ArmMmuEnabled)\r | |
31 | GCC_ASM_EXPORT (ArmEnableDataCache)\r | |
32 | GCC_ASM_EXPORT (ArmDisableDataCache)\r | |
33 | GCC_ASM_EXPORT (ArmEnableInstructionCache)\r | |
34 | GCC_ASM_EXPORT (ArmDisableInstructionCache)\r | |
35 | GCC_ASM_EXPORT (ArmEnableSWPInstruction)\r | |
36 | GCC_ASM_EXPORT (ArmEnableBranchPrediction)\r | |
37 | GCC_ASM_EXPORT (ArmDisableBranchPrediction)\r | |
38 | GCC_ASM_EXPORT (ArmSetLowVectors)\r | |
39 | GCC_ASM_EXPORT (ArmSetHighVectors)\r | |
40 | GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)\r | |
41 | GCC_ASM_EXPORT (ArmDataMemoryBarrier)\r | |
cf93a378 | 42 | GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)\r |
bd6b9799 | 43 | GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r |
836c3500 | 44 | GCC_ASM_EXPORT (ArmReadVBar)\r |
bd6b9799 | 45 | GCC_ASM_EXPORT (ArmWriteVBar)\r |
46 | GCC_ASM_EXPORT (ArmEnableVFP)\r | |
47 | GCC_ASM_EXPORT (ArmCallWFI)\r | |
48 | GCC_ASM_EXPORT (ArmReadCbar)\r | |
bd6b9799 | 49 | GCC_ASM_EXPORT (ArmReadMpidr)\r |
50 | GCC_ASM_EXPORT (ArmReadTpidrurw)\r | |
51 | GCC_ASM_EXPORT (ArmWriteTpidrurw)\r | |
52 | GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r | |
53 | GCC_ASM_EXPORT (ArmReadIdPfr1)\r | |
63dbd629 | 54 | GCC_ASM_EXPORT (ArmReadIdMmfr0)\r |
bd6b9799 | 55 | \r |
56 | .set DC_ON, (0x1<<2)\r | |
57 | .set IC_ON, (0x1<<12)\r | |
58 | .set CTRL_M_BIT, (1 << 0)\r | |
59 | .set CTRL_C_BIT, (1 << 2)\r | |
60 | .set CTRL_B_BIT, (1 << 7)\r | |
61 | .set CTRL_I_BIT, (1 << 12)\r | |
62 | \r | |
63 | \r | |
64 | ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r | |
3402aac7 | 65 | mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r |
bd6b9799 | 66 | bx lr\r |
67 | \r | |
68 | ASM_PFX(ArmCleanDataCacheEntryByMVA):\r | |
3402aac7 | 69 | mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r |
bd6b9799 | 70 | bx lr\r |
71 | \r | |
72 | \r | |
b7de7e3c EC |
73 | ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):\r |
74 | mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU\r | |
75 | bx lr\r | |
76 | \r | |
77 | \r | |
bd6b9799 | 78 | ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r |
79 | mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r | |
bd6b9799 | 80 | bx lr\r |
81 | \r | |
82 | \r | |
83 | ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):\r | |
3402aac7 | 84 | mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\r |
bd6b9799 | 85 | bx lr\r |
86 | \r | |
87 | \r | |
88 | ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):\r | |
3402aac7 | 89 | mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\r |
bd6b9799 | 90 | bx lr\r |
91 | \r | |
92 | \r | |
93 | ASM_PFX(ArmCleanDataCacheEntryBySetWay):\r | |
3402aac7 | 94 | mcr p15, 0, r0, c7, c10, 2 @ Clean this line\r |
bd6b9799 | 95 | bx lr\r |
96 | \r | |
97 | ASM_PFX(ArmInvalidateInstructionCache):\r | |
98 | mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache\r | |
99 | dsb\r | |
100 | isb\r | |
101 | bx LR\r | |
102 | \r | |
103 | ASM_PFX(ArmEnableMmu):\r | |
104 | mrc p15,0,R0,c1,c0,0\r | |
105 | orr R0,R0,#1\r | |
106 | mcr p15,0,R0,c1,c0,0\r | |
107 | dsb\r | |
108 | isb\r | |
109 | bx LR\r | |
110 | \r | |
111 | \r | |
112 | ASM_PFX(ArmDisableMmu):\r | |
113 | mrc p15,0,R0,c1,c0,0\r | |
114 | bic R0,R0,#1\r | |
115 | mcr p15,0,R0,c1,c0,0 @Disable MMU\r | |
116 | \r | |
117 | mcr p15,0,R0,c8,c7,0 @Invalidate TLB\r | |
118 | mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array\r | |
119 | dsb\r | |
120 | isb\r | |
121 | bx LR\r | |
122 | \r | |
123 | ASM_PFX(ArmDisableCachesAndMmu):\r | |
124 | mrc p15, 0, r0, c1, c0, 0 @ Get control register\r | |
125 | bic r0, r0, #CTRL_M_BIT @ Disable MMU\r | |
126 | bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r | |
127 | bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r | |
128 | mcr p15, 0, r0, c1, c0, 0 @ Write control register\r | |
129 | dsb\r | |
130 | isb\r | |
131 | bx LR\r | |
132 | \r | |
133 | ASM_PFX(ArmMmuEnabled):\r | |
134 | mrc p15,0,R0,c1,c0,0\r | |
135 | and R0,R0,#1\r | |
3402aac7 | 136 | bx LR\r |
bd6b9799 | 137 | \r |
138 | ASM_PFX(ArmEnableDataCache):\r | |
139 | ldr R1,=DC_ON\r | |
140 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
141 | orr R0,R0,R1 @Set C bit\r | |
142 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
143 | dsb\r | |
144 | isb\r | |
145 | bx LR\r | |
3402aac7 | 146 | \r |
bd6b9799 | 147 | ASM_PFX(ArmDisableDataCache):\r |
148 | ldr R1,=DC_ON\r | |
149 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
150 | bic R0,R0,R1 @Clear C bit\r | |
151 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
152 | dsb\r | |
153 | isb\r | |
154 | bx LR\r | |
155 | \r | |
156 | ASM_PFX(ArmEnableInstructionCache):\r | |
157 | ldr R1,=IC_ON\r | |
158 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
159 | orr R0,R0,R1 @Set I bit\r | |
160 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
161 | dsb\r | |
162 | isb\r | |
163 | bx LR\r | |
3402aac7 | 164 | \r |
bd6b9799 | 165 | ASM_PFX(ArmDisableInstructionCache):\r |
166 | ldr R1,=IC_ON\r | |
167 | mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r | |
168 | bic R0,R0,R1 @Clear I bit.\r | |
169 | mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r | |
170 | dsb\r | |
171 | isb\r | |
172 | bx LR\r | |
173 | \r | |
174 | ASM_PFX(ArmEnableSWPInstruction):\r | |
175 | mrc p15, 0, r0, c1, c0, 0\r | |
176 | orr r0, r0, #0x00000400\r | |
177 | mcr p15, 0, r0, c1, c0, 0\r | |
178 | isb\r | |
179 | bx LR\r | |
180 | \r | |
181 | ASM_PFX(ArmEnableBranchPrediction):\r | |
182 | mrc p15, 0, r0, c1, c0, 0\r | |
183 | orr r0, r0, #0x00000800\r | |
184 | mcr p15, 0, r0, c1, c0, 0\r | |
185 | dsb\r | |
186 | isb\r | |
187 | bx LR\r | |
188 | \r | |
189 | ASM_PFX(ArmDisableBranchPrediction):\r | |
190 | mrc p15, 0, r0, c1, c0, 0\r | |
191 | bic r0, r0, #0x00000800\r | |
192 | mcr p15, 0, r0, c1, c0, 0\r | |
193 | dsb\r | |
194 | isb\r | |
195 | bx LR\r | |
196 | \r | |
197 | ASM_PFX(ArmSetLowVectors):\r | |
198 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r | |
199 | bic r0, r0, #0x00002000 @ clear V bit\r | |
200 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r | |
201 | isb\r | |
202 | bx LR\r | |
203 | \r | |
204 | ASM_PFX(ArmSetHighVectors):\r | |
205 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r | |
c6ba1c12 | 206 | orr r0, r0, #0x00002000 @ Set V bit\r |
bd6b9799 | 207 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r |
208 | isb\r | |
209 | bx LR\r | |
210 | \r | |
211 | ASM_PFX(ArmV7AllDataCachesOperation):\r | |
212 | stmfd SP!,{r4-r12, LR}\r | |
213 | mov R1, R0 @ Save Function call in R1\r | |
214 | mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR\r | |
215 | ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)\r | |
216 | mov R3, R3, LSR #23 @ Cache level value (naturally aligned)\r | |
217 | beq L_Finished\r | |
218 | mov R10, #0\r | |
219 | \r | |
3402aac7 | 220 | Loop1:\r |
bd6b9799 | 221 | add R2, R10, R10, LSR #1 @ Work out 3xcachelevel\r |
222 | mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level\r | |
223 | and R12, R12, #7 @ get those 3 bits alone\r | |
224 | cmp R12, #2\r | |
225 | blt L_Skip @ no cache or only instruction cache at this level\r | |
226 | mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r | |
3402aac7 | 227 | isb @ isb to sync the change to the CacheSizeID reg\r |
bd6b9799 | 228 | mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)\r |
229 | and R2, R12, #0x7 @ extract the line length field\r | |
230 | add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)\r | |
231 | @ ldr R4, =0x3FF\r | |
232 | mov R4, #0x400\r | |
233 | sub R4, R4, #1\r | |
234 | ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)\r | |
235 | clz R5, R4 @ R5 is the bit position of the way size increment\r | |
236 | @ ldr R7, =0x00007FFF\r | |
237 | mov R7, #0x00008000\r | |
238 | sub R7, R7, #1\r | |
239 | ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)\r | |
240 | \r | |
3402aac7 | 241 | Loop2:\r |
bd6b9799 | 242 | mov R9, R4 @ R9 working copy of the max way size (right aligned)\r |
243 | \r | |
3402aac7 | 244 | Loop3:\r |
bd6b9799 | 245 | orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11\r |
246 | orr R0, R0, R7, LSL R2 @ factor in the index number\r | |
247 | \r | |
248 | blx R1\r | |
249 | \r | |
250 | subs R9, R9, #1 @ decrement the way number\r | |
251 | bge Loop3\r | |
252 | subs R7, R7, #1 @ decrement the index\r | |
253 | bge Loop2\r | |
3402aac7 | 254 | L_Skip:\r |
bd6b9799 | 255 | add R10, R10, #2 @ increment the cache number\r |
256 | cmp R3, R10\r | |
257 | bgt Loop1\r | |
3402aac7 | 258 | \r |
bd6b9799 | 259 | L_Finished:\r |
260 | dsb\r | |
261 | ldmfd SP!, {r4-r12, lr}\r | |
262 | bx LR\r | |
263 | \r | |
264 | ASM_PFX(ArmDataMemoryBarrier):\r | |
265 | dmb\r | |
266 | bx LR\r | |
3402aac7 | 267 | \r |
cf93a378 | 268 | ASM_PFX(ArmDataSynchronizationBarrier):\r |
bd6b9799 | 269 | dsb\r |
270 | bx LR\r | |
3402aac7 | 271 | \r |
bd6b9799 | 272 | ASM_PFX(ArmInstructionSynchronizationBarrier):\r |
273 | isb\r | |
274 | bx LR\r | |
275 | \r | |
836c3500 | 276 | ASM_PFX(ArmReadVBar):\r |
277 | # Set the Address of the Vector Table in the VBAR register\r | |
278 | mrc p15, 0, r0, c12, c0, 0\r | |
279 | bx lr\r | |
280 | \r | |
bd6b9799 | 281 | ASM_PFX(ArmWriteVBar):\r |
282 | # Set the Address of the Vector Table in the VBAR register\r | |
3402aac7 | 283 | mcr p15, 0, r0, c12, c0, 0\r |
bd6b9799 | 284 | # Ensure the SCTLR.V bit is clear\r |
285 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r | |
286 | bic r0, r0, #0x00002000 @ clear V bit\r | |
287 | mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r | |
288 | isb\r | |
289 | bx lr\r | |
290 | \r | |
291 | ASM_PFX(ArmEnableVFP):\r | |
292 | # Read CPACR (Coprocessor Access Control Register)\r | |
293 | mrc p15, 0, r0, c1, c0, 2\r | |
294 | # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r | |
295 | orr r0, r0, #0x00f00000\r | |
296 | # Write back CPACR (Coprocessor Access Control Register)\r | |
297 | mcr p15, 0, r0, c1, c0, 2\r | |
18029bb9 | 298 | isb\r |
bd6b9799 | 299 | # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r |
300 | mov r0, #0x40000000\r | |
301 | mcr p10,#0x7,r0,c8,c0,#0\r | |
302 | bx lr\r | |
303 | \r | |
304 | ASM_PFX(ArmCallWFI):\r | |
305 | wfi\r | |
306 | bx lr\r | |
307 | \r | |
308 | #Note: Return 0 in Uniprocessor implementation\r | |
309 | ASM_PFX(ArmReadCbar):\r | |
310 | mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register\r | |
311 | bx lr\r | |
312 | \r | |
bd6b9799 | 313 | ASM_PFX(ArmReadMpidr):\r |
314 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r | |
315 | bx lr\r | |
3402aac7 | 316 | \r |
bd6b9799 | 317 | ASM_PFX(ArmReadTpidrurw):\r |
318 | mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r | |
319 | bx lr\r | |
320 | \r | |
321 | ASM_PFX(ArmWriteTpidrurw):\r | |
322 | mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW\r | |
323 | bx lr\r | |
324 | \r | |
325 | ASM_PFX(ArmIsArchTimerImplemented):\r | |
326 | mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1\r | |
327 | and r0, r0, #0x000F0000\r | |
328 | bx lr\r | |
329 | \r | |
330 | ASM_PFX(ArmReadIdPfr1):\r | |
331 | mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register\r | |
332 | bx lr\r | |
333 | \r | |
63dbd629 AB |
334 | ASM_PFX(ArmReadIdMmfr0):\r |
335 | mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register\r | |
336 | bx lr\r | |
337 | \r | |
bd6b9799 | 338 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |