[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

//------------------------------------------------------------------------------\r
//\r
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution.  The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//------------------------------------------------------------------------------\r
\r
    EXPORT  ArmInvalidateInstructionCache\r
    EXPORT  ArmInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmCleanDataCacheEntryByMVA\r
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmInvalidateDataCacheEntryBySetWay\r
    EXPORT  ArmCleanDataCacheEntryBySetWay\r
    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay\r
    EXPORT  ArmEnableMmu\r
    EXPORT  ArmDisableMmu\r
    EXPORT  ArmDisableCachesAndMmu\r
    EXPORT  ArmMmuEnabled\r
    EXPORT  ArmEnableDataCache\r
    EXPORT  ArmDisableDataCache\r
    EXPORT  ArmEnableInstructionCache\r
    EXPORT  ArmDisableInstructionCache\r
    EXPORT  ArmEnableSWPInstruction\r
    EXPORT  ArmEnableBranchPrediction\r
    EXPORT  ArmDisableBranchPrediction\r
    EXPORT  ArmSetLowVectors\r
    EXPORT  ArmSetHighVectors\r
    EXPORT  ArmV7AllDataCachesOperation\r
    EXPORT  ArmDataMemoryBarrier\r
    EXPORT  ArmDataSynchronizationBarrier\r
    EXPORT  ArmInstructionSynchronizationBarrier\r
    EXPORT  ArmReadVBar\r
    EXPORT  ArmWriteVBar\r
    EXPORT  ArmEnableVFP\r
    EXPORT  ArmCallWFI\r
    EXPORT  ArmReadCbar\r
    EXPORT  ArmReadMpidr\r
    EXPORT  ArmReadTpidrurw\r
    EXPORT  ArmWriteTpidrurw\r
    EXPORT  ArmIsArchTimerImplemented\r
    EXPORT  ArmReadIdPfr1\r
    EXPORT  ArmReadIdMmfr0\r
\r
    AREA    ArmV7Support, CODE, READONLY\r
    PRESERVE8\r
\r
DC_ON           EQU     ( 0x1:SHL:2 )\r
IC_ON           EQU     ( 0x1:SHL:12 )\r
CTRL_M_BIT      EQU     (1 << 0)\r
CTRL_C_BIT      EQU     (1 << 2)\r
CTRL_B_BIT      EQU     (1 << 7)\r
CTRL_I_BIT      EQU     (1 << 12)\r
\r
\r
ArmInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
  bx      lr\r
\r
ArmCleanDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
  bx      lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
  bx      lr\r
\r
\r
ArmInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line\r
  bx      lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line\r
  bx      lr\r
\r
\r
ArmCleanDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line\r
  bx      lr\r
\r
\r
ArmInvalidateInstructionCache\r
  mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache\r
  isb\r
  bx      LR\r
\r
ArmEnableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
\r
  mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB\r
  mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableCachesAndMmu\r
  mrc   p15, 0, r0, c1, c0, 0           ; Get control register\r
  bic   r0, r0, #CTRL_M_BIT             ; Disable MMU\r
  bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache\r
  bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache\r
  mcr   p15, 0, r0, c1, c0, 0           ; Write control register\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmMmuEnabled\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  and     R0,R0,#1\r
  bx      LR\r
\r
ArmEnableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmEnableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmEnableSWPInstruction\r
  mrc     p15, 0, r0, c1, c0, 0\r
  orr     r0, r0, #0x00000400\r
  mcr     p15, 0, r0, c1, c0, 0\r
  isb\r
  bx      LR\r
\r
ArmEnableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmSetLowVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmSetHighVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00002000   ; Set V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmV7AllDataCachesOperation\r
  stmfd SP!,{r4-r12, LR}\r
  mov   R1, R0                ; Save Function call in R1\r
  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
  ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)\r
  mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)\r
  beq   Finished\r
  mov   R10, #0\r
\r
Loop1\r
  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel\r
  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level\r
  and   R12, R12, #7            ; get those 3 bits alone\r
  cmp   R12, #2\r
  blt   Skip                    ; no cache or only instruction cache at this level\r
  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
  isb                           ; isb to sync the change to the CacheSizeID reg\r
  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)\r
  and   R2, R12, #&7            ; extract the line length field\r
  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)\r
  ldr   R4, =0x3FF\r
  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)\r
  clz   R5, R4                  ; R5 is the bit position of the way size increment\r
  ldr   R7, =0x00007FFF\r
  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)\r
\r
Loop2\r
  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)\r
\r
Loop3\r
  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11\r
  orr   R0, R0, R7, LSL R2      ; factor in the index number\r
\r
  blx   R1\r
\r
  subs  R9, R9, #1              ; decrement the way number\r
  bge   Loop3\r
  subs  R7, R7, #1              ; decrement the index\r
  bge   Loop2\r
Skip\r
  add   R10, R10, #2            ; increment the cache number\r
  cmp   R3, R10\r
  bgt   Loop1\r
\r
Finished\r
  dsb\r
  ldmfd SP!, {r4-r12, lr}\r
  bx    LR\r
\r
ArmDataMemoryBarrier\r
  dmb\r
  bx      LR\r
\r
ArmDataSynchronizationBarrier\r
  dsb\r
  bx      LR\r
\r
ArmInstructionSynchronizationBarrier\r
  isb\r
  bx      LR\r
\r
ArmReadVBar\r
  // Set the Address of the Vector Table in the VBAR register\r
  mrc     p15, 0, r0, c12, c0, 0\r
  bx      lr\r
\r
ArmWriteVBar\r
  // Set the Address of the Vector Table in the VBAR register\r
  mcr     p15, 0, r0, c12, c0, 0\r
  // Ensure the SCTLR.V bit is clear\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      lr\r
\r
ArmEnableVFP\r
  // Read CPACR (Coprocessor Access Control Register)\r
  mrc     p15, 0, r0, c1, c0, 2\r
  // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
  orr     r0, r0, #0x00f00000\r
  // Write back CPACR (Coprocessor Access Control Register)\r
  mcr     p15, 0, r0, c1, c0, 2\r
  isb\r
  // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
  mov     r0, #0x40000000\r
  mcr     p10,#0x7,r0,c8,c0,#0\r
  bx      lr\r
\r
ArmCallWFI\r
  wfi\r
  bx      lr\r
\r
//Note: Return 0 in Uniprocessor implementation\r
ArmReadCbar\r
  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register\r
  bx      lr\r
\r
ArmReadMpidr\r
  mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR\r
  bx      lr\r
\r
ArmReadTpidrurw\r
  mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW\r
  bx      lr\r
\r
ArmWriteTpidrurw\r
  mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW\r
  bx      lr\r
\r
ArmIsArchTimerImplemented\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1\r
  and    r0, r0, #0x000F0000\r
  bx     lr\r
\r
ArmReadIdPfr1\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register\r
  bx     lr\r
\r
ArmReadIdMmfr0\r
  mrc    p15, 0, r0, c0, c1, 4     ; Read ID_MMFR0 Register\r
  bx     lr\r
\r
 END\r
Commit	Line	Data
3402aac7	1	//------------------------------------------------------------------------------\r
bd6b9799	2	//\r
bd6b9799	3	// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
9401d6f4	4	// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
bd6b9799	5	//\r
	6	// This program and the accompanying materials\r
	7	// are licensed and made available under the terms and conditions of the BSD License\r
	8	// which accompanies this distribution. The full text of the license may be found at\r
	9	// http://opensource.org/licenses/bsd-license.php\r
	10	//\r
	11	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	//\r
	14	//------------------------------------------------------------------------------\r
	15	\r
	16	EXPORT ArmInvalidateInstructionCache\r
	17	EXPORT ArmInvalidateDataCacheEntryByMVA\r
	18	EXPORT ArmCleanDataCacheEntryByMVA\r
	19	EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
	20	EXPORT ArmInvalidateDataCacheEntryBySetWay\r
	21	EXPORT ArmCleanDataCacheEntryBySetWay\r
	22	EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
bd6b9799	23	EXPORT ArmEnableMmu\r
	24	EXPORT ArmDisableMmu\r
	25	EXPORT ArmDisableCachesAndMmu\r
	26	EXPORT ArmMmuEnabled\r
	27	EXPORT ArmEnableDataCache\r
	28	EXPORT ArmDisableDataCache\r
	29	EXPORT ArmEnableInstructionCache\r
	30	EXPORT ArmDisableInstructionCache\r
	31	EXPORT ArmEnableSWPInstruction\r
	32	EXPORT ArmEnableBranchPrediction\r
	33	EXPORT ArmDisableBranchPrediction\r
	34	EXPORT ArmSetLowVectors\r
	35	EXPORT ArmSetHighVectors\r
	36	EXPORT ArmV7AllDataCachesOperation\r
	37	EXPORT ArmDataMemoryBarrier\r
cf93a378	38	EXPORT ArmDataSynchronizationBarrier\r
bd6b9799	39	EXPORT ArmInstructionSynchronizationBarrier\r
836c3500	40	EXPORT ArmReadVBar\r
bd6b9799	41	EXPORT ArmWriteVBar\r
	42	EXPORT ArmEnableVFP\r
	43	EXPORT ArmCallWFI\r
	44	EXPORT ArmReadCbar\r
bd6b9799	45	EXPORT ArmReadMpidr\r
	46	EXPORT ArmReadTpidrurw\r
	47	EXPORT ArmWriteTpidrurw\r
	48	EXPORT ArmIsArchTimerImplemented\r
	49	EXPORT ArmReadIdPfr1\r
63dbd629	50	EXPORT ArmReadIdMmfr0\r
bd6b9799	51	\r
	52	AREA ArmV7Support, CODE, READONLY\r
	53	PRESERVE8\r
	54	\r
	55	DC_ON EQU ( 0x1:SHL:2 )\r
	56	IC_ON EQU ( 0x1:SHL:12 )\r
	57	CTRL_M_BIT EQU (1 << 0)\r
	58	CTRL_C_BIT EQU (1 << 2)\r
	59	CTRL_B_BIT EQU (1 << 7)\r
	60	CTRL_I_BIT EQU (1 << 12)\r
	61	\r
	62	\r
	63	ArmInvalidateDataCacheEntryByMVA\r
3402aac7	64	mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
bd6b9799	65	bx lr\r
	66	\r
	67	ArmCleanDataCacheEntryByMVA\r
3402aac7	68	mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
bd6b9799	69	bx lr\r
	70	\r
	71	\r
	72	ArmCleanInvalidateDataCacheEntryByMVA\r
	73	mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
bd6b9799	74	bx lr\r
	75	\r
	76	\r
	77	ArmInvalidateDataCacheEntryBySetWay\r
3402aac7	78	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r
bd6b9799	79	bx lr\r
	80	\r
	81	\r
	82	ArmCleanInvalidateDataCacheEntryBySetWay\r
3402aac7	83	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r
bd6b9799	84	bx lr\r
	85	\r
	86	\r
	87	ArmCleanDataCacheEntryBySetWay\r
3402aac7	88	mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r
bd6b9799	89	bx lr\r
	90	\r
	91	\r
	92	ArmInvalidateInstructionCache\r
	93	mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
	94	isb\r
	95	bx LR\r
	96	\r
	97	ArmEnableMmu\r
	98	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	99	orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
	100	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	101	dsb\r
	102	isb\r
	103	bx LR\r
	104	\r
	105	ArmDisableMmu\r
	106	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	107	bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
	108	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	109	\r
	110	mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
	111	mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
	112	dsb\r
	113	isb\r
	114	bx LR\r
	115	\r
	116	ArmDisableCachesAndMmu\r
	117	mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
	118	bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
	119	bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
	120	bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
	121	mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
	122	dsb\r
	123	isb\r
	124	bx LR\r
	125	\r
	126	ArmMmuEnabled\r
	127	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	128	and R0,R0,#1\r
	129	bx LR\r
	130	\r
	131	ArmEnableDataCache\r
	132	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
	133	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	134	orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
	135	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	136	dsb\r
	137	isb\r
	138	bx LR\r
3402aac7	139	\r
bd6b9799	140	ArmDisableDataCache\r
	141	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
	142	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	143	bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
	144	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	145	dsb\r
	146	isb\r
	147	bx LR\r
	148	\r
	149	ArmEnableInstructionCache\r
	150	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
	151	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	152	orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
	153	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	154	dsb\r
	155	isb\r
	156	bx LR\r
3402aac7	157	\r
bd6b9799	158	ArmDisableInstructionCache\r
	159	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
	160	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
	161	BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
	162	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
	163	isb\r
	164	bx LR\r
	165	\r
	166	ArmEnableSWPInstruction\r
	167	mrc p15, 0, r0, c1, c0, 0\r
	168	orr r0, r0, #0x00000400\r
	169	mcr p15, 0, r0, c1, c0, 0\r
	170	isb\r
	171	bx LR\r
	172	\r
	173	ArmEnableBranchPrediction\r
	174	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	175	orr r0, r0, #0x00000800 ;\r
	176	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	177	dsb\r
	178	isb\r
	179	bx LR\r
	180	\r
	181	ArmDisableBranchPrediction\r
	182	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	183	bic r0, r0, #0x00000800 ;\r
	184	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	185	dsb\r
	186	isb\r
	187	bx LR\r
	188	\r
	189	ArmSetLowVectors\r
	190	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	191	bic r0, r0, #0x00002000 ; clear V bit\r
	192	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	193	isb\r
	194	bx LR\r
	195	\r
	196	ArmSetHighVectors\r
	197	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
c6ba1c12	198	orr r0, r0, #0x00002000 ; Set V bit\r
bd6b9799	199	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	200	isb\r
	201	bx LR\r
	202	\r
	203	ArmV7AllDataCachesOperation\r
	204	stmfd SP!,{r4-r12, LR}\r
	205	mov R1, R0 ; Save Function call in R1\r
	206	mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
	207	ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
	208	mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
	209	beq Finished\r
	210	mov R10, #0\r
	211	\r
3402aac7	212	Loop1\r
bd6b9799	213	add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
	214	mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
	215	and R12, R12, #7 ; get those 3 bits alone\r
	216	cmp R12, #2\r
	217	blt Skip ; no cache or only instruction cache at this level\r
	218	mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
3402aac7	219	isb ; isb to sync the change to the CacheSizeID reg\r
bd6b9799	220	mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
	221	and R2, R12, #&7 ; extract the line length field\r
	222	add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
	223	ldr R4, =0x3FF\r
	224	ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
	225	clz R5, R4 ; R5 is the bit position of the way size increment\r
	226	ldr R7, =0x00007FFF\r
	227	ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
	228	\r
3402aac7	229	Loop2\r
bd6b9799	230	mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
bd6b9799	231	\r
3402aac7	232	Loop3\r
bd6b9799	233	orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
	234	orr R0, R0, R7, LSL R2 ; factor in the index number\r
	235	\r
	236	blx R1\r
	237	\r
	238	subs R9, R9, #1 ; decrement the way number\r
	239	bge Loop3\r
	240	subs R7, R7, #1 ; decrement the index\r
	241	bge Loop2\r
3402aac7	242	Skip\r
bd6b9799	243	add R10, R10, #2 ; increment the cache number\r
	244	cmp R3, R10\r
	245	bgt Loop1\r
3402aac7	246	\r
bd6b9799	247	Finished\r
	248	dsb\r
	249	ldmfd SP!, {r4-r12, lr}\r
	250	bx LR\r
	251	\r
	252	ArmDataMemoryBarrier\r
	253	dmb\r
	254	bx LR\r
3402aac7	255	\r
cf93a378	256	ArmDataSynchronizationBarrier\r
bd6b9799	257	dsb\r
bd6b9799	258	bx LR\r
3402aac7	259	\r
bd6b9799	260	ArmInstructionSynchronizationBarrier\r
	261	isb\r
	262	bx LR\r
	263	\r
836c3500	264	ArmReadVBar\r
	265	// Set the Address of the Vector Table in the VBAR register\r
	266	mrc p15, 0, r0, c12, c0, 0\r
	267	bx lr\r
	268	\r
bd6b9799	269	ArmWriteVBar\r
bd6b9799	270	// Set the Address of the Vector Table in the VBAR register\r
3402aac7	271	mcr p15, 0, r0, c12, c0, 0\r
bd6b9799	272	// Ensure the SCTLR.V bit is clear\r
	273	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
	274	bic r0, r0, #0x00002000 ; clear V bit\r
	275	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
	276	isb\r
	277	bx lr\r
	278	\r
	279	ArmEnableVFP\r
	280	// Read CPACR (Coprocessor Access Control Register)\r
	281	mrc p15, 0, r0, c1, c0, 2\r
	282	// Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
	283	orr r0, r0, #0x00f00000\r
	284	// Write back CPACR (Coprocessor Access Control Register)\r
	285	mcr p15, 0, r0, c1, c0, 2\r
18029bb9	286	isb\r
bd6b9799	287	// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
	288	mov r0, #0x40000000\r
	289	mcr p10,#0x7,r0,c8,c0,#0\r
	290	bx lr\r
	291	\r
	292	ArmCallWFI\r
	293	wfi\r
	294	bx lr\r
	295	\r
	296	//Note: Return 0 in Uniprocessor implementation\r
	297	ArmReadCbar\r
	298	mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
	299	bx lr\r
	300	\r
bd6b9799	301	ArmReadMpidr\r
	302	mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
	303	bx lr\r
	304	\r
	305	ArmReadTpidrurw\r
	306	mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
	307	bx lr\r
	308	\r
	309	ArmWriteTpidrurw\r
	310	mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
	311	bx lr\r
	312	\r
	313	ArmIsArchTimerImplemented\r
	314	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
	315	and r0, r0, #0x000F0000\r
	316	bx lr\r
	317	\r
	318	ArmReadIdPfr1\r
	319	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
	320	bx lr\r
	321	\r
63dbd629 AB	322	ArmReadIdMmfr0\r
	323	mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register\r
	324	bx lr\r
	325	\r
bd6b9799	326	END\r