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3402aac7 | 1 | //------------------------------------------------------------------------------\r |
bd6b9799 | 2 | //\r |
3 | // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
9401d6f4 | 4 | // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | //\r |
6 | // This program and the accompanying materials\r | |
7 | // are licensed and made available under the terms and conditions of the BSD License\r | |
8 | // which accompanies this distribution. The full text of the license may be found at\r | |
9 | // http://opensource.org/licenses/bsd-license.php\r | |
10 | //\r | |
11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | //\r | |
14 | //------------------------------------------------------------------------------\r | |
15 | \r | |
efda1775 EC |
16 | \r |
17 | INCLUDE AsmMacroExport.inc\r | |
bd6b9799 | 18 | PRESERVE8\r |
19 | \r | |
20 | DC_ON EQU ( 0x1:SHL:2 )\r | |
21 | IC_ON EQU ( 0x1:SHL:12 )\r | |
22 | CTRL_M_BIT EQU (1 << 0)\r | |
23 | CTRL_C_BIT EQU (1 << 2)\r | |
24 | CTRL_B_BIT EQU (1 << 7)\r | |
25 | CTRL_I_BIT EQU (1 << 12)\r | |
26 | \r | |
27 | \r | |
efda1775 | 28 | RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA\r |
3402aac7 | 29 | mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r |
bd6b9799 | 30 | bx lr\r |
31 | \r | |
efda1775 | 32 | RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA\r |
3402aac7 | 33 | mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r |
bd6b9799 | 34 | bx lr\r |
35 | \r | |
36 | \r | |
cf580da1 AB |
37 | RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA\r |
38 | mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU\r | |
39 | mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor\r | |
40 | bx lr\r | |
41 | \r | |
42 | \r | |
b7de7e3c EC |
43 | RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA\r |
44 | mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU\r | |
45 | bx lr\r | |
46 | \r | |
47 | \r | |
efda1775 | 48 | RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r |
bd6b9799 | 49 | mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r |
bd6b9799 | 50 | bx lr\r |
51 | \r | |
52 | \r | |
efda1775 | 53 | RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay\r |
3402aac7 | 54 | mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\r |
bd6b9799 | 55 | bx lr\r |
56 | \r | |
57 | \r | |
efda1775 | 58 | RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r |
3402aac7 | 59 | mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\r |
bd6b9799 | 60 | bx lr\r |
61 | \r | |
62 | \r | |
efda1775 | 63 | RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay\r |
3402aac7 | 64 | mcr p15, 0, r0, c7, c10, 2 ; Clean this line\r |
bd6b9799 | 65 | bx lr\r |
66 | \r | |
67 | \r | |
efda1775 | 68 | RVCT_ASM_EXPORT ArmInvalidateInstructionCache\r |
bd6b9799 | 69 | mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r |
70 | isb\r | |
71 | bx LR\r | |
72 | \r | |
efda1775 | 73 | RVCT_ASM_EXPORT ArmEnableMmu\r |
bd6b9799 | 74 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r |
75 | orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r | |
76 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
77 | dsb\r | |
78 | isb\r | |
79 | bx LR\r | |
80 | \r | |
efda1775 | 81 | RVCT_ASM_EXPORT ArmDisableMmu\r |
bd6b9799 | 82 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r |
83 | bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r | |
84 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
85 | \r | |
86 | mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r | |
87 | mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r | |
88 | dsb\r | |
89 | isb\r | |
90 | bx LR\r | |
91 | \r | |
efda1775 | 92 | RVCT_ASM_EXPORT ArmDisableCachesAndMmu\r |
bd6b9799 | 93 | mrc p15, 0, r0, c1, c0, 0 ; Get control register\r |
94 | bic r0, r0, #CTRL_M_BIT ; Disable MMU\r | |
95 | bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r | |
96 | bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r | |
97 | mcr p15, 0, r0, c1, c0, 0 ; Write control register\r | |
98 | dsb\r | |
99 | isb\r | |
100 | bx LR\r | |
101 | \r | |
efda1775 | 102 | RVCT_ASM_EXPORT ArmMmuEnabled\r |
bd6b9799 | 103 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r |
104 | and R0,R0,#1\r | |
105 | bx LR\r | |
106 | \r | |
efda1775 | 107 | RVCT_ASM_EXPORT ArmEnableDataCache\r |
bd6b9799 | 108 | ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r |
109 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
110 | orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r | |
111 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
112 | dsb\r | |
113 | isb\r | |
114 | bx LR\r | |
3402aac7 | 115 | \r |
efda1775 | 116 | RVCT_ASM_EXPORT ArmDisableDataCache\r |
bd6b9799 | 117 | ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r |
118 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
119 | bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r | |
120 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
121 | dsb\r | |
122 | isb\r | |
123 | bx LR\r | |
124 | \r | |
efda1775 | 125 | RVCT_ASM_EXPORT ArmEnableInstructionCache\r |
bd6b9799 | 126 | ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r |
127 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
128 | orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r | |
129 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
130 | dsb\r | |
131 | isb\r | |
132 | bx LR\r | |
3402aac7 | 133 | \r |
efda1775 | 134 | RVCT_ASM_EXPORT ArmDisableInstructionCache\r |
bd6b9799 | 135 | ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r |
136 | mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
137 | BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r | |
138 | mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
139 | isb\r | |
140 | bx LR\r | |
141 | \r | |
efda1775 | 142 | RVCT_ASM_EXPORT ArmEnableSWPInstruction\r |
bd6b9799 | 143 | mrc p15, 0, r0, c1, c0, 0\r |
144 | orr r0, r0, #0x00000400\r | |
145 | mcr p15, 0, r0, c1, c0, 0\r | |
146 | isb\r | |
147 | bx LR\r | |
148 | \r | |
efda1775 | 149 | RVCT_ASM_EXPORT ArmEnableBranchPrediction\r |
bd6b9799 | 150 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
151 | orr r0, r0, #0x00000800 ;\r | |
152 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
153 | dsb\r | |
154 | isb\r | |
155 | bx LR\r | |
156 | \r | |
efda1775 | 157 | RVCT_ASM_EXPORT ArmDisableBranchPrediction\r |
bd6b9799 | 158 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
159 | bic r0, r0, #0x00000800 ;\r | |
160 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
161 | dsb\r | |
162 | isb\r | |
163 | bx LR\r | |
164 | \r | |
efda1775 | 165 | RVCT_ASM_EXPORT ArmSetLowVectors\r |
bd6b9799 | 166 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
167 | bic r0, r0, #0x00002000 ; clear V bit\r | |
168 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
169 | isb\r | |
170 | bx LR\r | |
171 | \r | |
efda1775 | 172 | RVCT_ASM_EXPORT ArmSetHighVectors\r |
bd6b9799 | 173 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r |
c6ba1c12 | 174 | orr r0, r0, #0x00002000 ; Set V bit\r |
bd6b9799 | 175 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r |
176 | isb\r | |
177 | bx LR\r | |
178 | \r | |
efda1775 | 179 | RVCT_ASM_EXPORT ArmV7AllDataCachesOperation\r |
bd6b9799 | 180 | stmfd SP!,{r4-r12, LR}\r |
181 | mov R1, R0 ; Save Function call in R1\r | |
182 | mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r | |
183 | ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r | |
184 | mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r | |
185 | beq Finished\r | |
186 | mov R10, #0\r | |
187 | \r | |
3402aac7 | 188 | Loop1\r |
bd6b9799 | 189 | add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r |
190 | mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r | |
191 | and R12, R12, #7 ; get those 3 bits alone\r | |
192 | cmp R12, #2\r | |
193 | blt Skip ; no cache or only instruction cache at this level\r | |
194 | mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r | |
3402aac7 | 195 | isb ; isb to sync the change to the CacheSizeID reg\r |
bd6b9799 | 196 | mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r |
197 | and R2, R12, #&7 ; extract the line length field\r | |
198 | add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r | |
199 | ldr R4, =0x3FF\r | |
200 | ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r | |
201 | clz R5, R4 ; R5 is the bit position of the way size increment\r | |
202 | ldr R7, =0x00007FFF\r | |
203 | ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r | |
204 | \r | |
3402aac7 | 205 | Loop2\r |
bd6b9799 | 206 | mov R9, R4 ; R9 working copy of the max way size (right aligned)\r |
207 | \r | |
3402aac7 | 208 | Loop3\r |
bd6b9799 | 209 | orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r |
210 | orr R0, R0, R7, LSL R2 ; factor in the index number\r | |
211 | \r | |
212 | blx R1\r | |
213 | \r | |
214 | subs R9, R9, #1 ; decrement the way number\r | |
215 | bge Loop3\r | |
216 | subs R7, R7, #1 ; decrement the index\r | |
217 | bge Loop2\r | |
3402aac7 | 218 | Skip\r |
bd6b9799 | 219 | add R10, R10, #2 ; increment the cache number\r |
220 | cmp R3, R10\r | |
221 | bgt Loop1\r | |
3402aac7 | 222 | \r |
bd6b9799 | 223 | Finished\r |
224 | dsb\r | |
225 | ldmfd SP!, {r4-r12, lr}\r | |
226 | bx LR\r | |
227 | \r | |
efda1775 | 228 | RVCT_ASM_EXPORT ArmDataMemoryBarrier\r |
bd6b9799 | 229 | dmb\r |
230 | bx LR\r | |
3402aac7 | 231 | \r |
efda1775 | 232 | RVCT_ASM_EXPORT ArmDataSynchronizationBarrier\r |
bd6b9799 | 233 | dsb\r |
234 | bx LR\r | |
3402aac7 | 235 | \r |
efda1775 | 236 | RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier\r |
bd6b9799 | 237 | isb\r |
238 | bx LR\r | |
239 | \r | |
efda1775 | 240 | RVCT_ASM_EXPORT ArmReadVBar\r |
836c3500 | 241 | // Set the Address of the Vector Table in the VBAR register\r |
242 | mrc p15, 0, r0, c12, c0, 0\r | |
243 | bx lr\r | |
244 | \r | |
efda1775 | 245 | RVCT_ASM_EXPORT ArmWriteVBar\r |
bd6b9799 | 246 | // Set the Address of the Vector Table in the VBAR register\r |
3402aac7 | 247 | mcr p15, 0, r0, c12, c0, 0\r |
bd6b9799 | 248 | // Ensure the SCTLR.V bit is clear\r |
249 | mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r | |
250 | bic r0, r0, #0x00002000 ; clear V bit\r | |
251 | mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r | |
252 | isb\r | |
253 | bx lr\r | |
254 | \r | |
efda1775 | 255 | RVCT_ASM_EXPORT ArmEnableVFP\r |
bd6b9799 | 256 | // Read CPACR (Coprocessor Access Control Register)\r |
257 | mrc p15, 0, r0, c1, c0, 2\r | |
258 | // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r | |
259 | orr r0, r0, #0x00f00000\r | |
260 | // Write back CPACR (Coprocessor Access Control Register)\r | |
261 | mcr p15, 0, r0, c1, c0, 2\r | |
18029bb9 | 262 | isb\r |
bd6b9799 | 263 | // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r |
264 | mov r0, #0x40000000\r | |
265 | mcr p10,#0x7,r0,c8,c0,#0\r | |
266 | bx lr\r | |
267 | \r | |
efda1775 | 268 | RVCT_ASM_EXPORT ArmCallWFI\r |
bd6b9799 | 269 | wfi\r |
270 | bx lr\r | |
271 | \r | |
272 | //Note: Return 0 in Uniprocessor implementation\r | |
efda1775 | 273 | RVCT_ASM_EXPORT ArmReadCbar\r |
bd6b9799 | 274 | mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r |
275 | bx lr\r | |
276 | \r | |
efda1775 | 277 | RVCT_ASM_EXPORT ArmReadMpidr\r |
bd6b9799 | 278 | mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r |
279 | bx lr\r | |
280 | \r | |
efda1775 | 281 | RVCT_ASM_EXPORT ArmReadTpidrurw\r |
bd6b9799 | 282 | mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r |
283 | bx lr\r | |
284 | \r | |
efda1775 | 285 | RVCT_ASM_EXPORT ArmWriteTpidrurw\r |
bd6b9799 | 286 | mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r |
287 | bx lr\r | |
288 | \r | |
efda1775 | 289 | RVCT_ASM_EXPORT ArmIsArchTimerImplemented\r |
bd6b9799 | 290 | mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r |
291 | and r0, r0, #0x000F0000\r | |
292 | bx lr\r | |
293 | \r | |
efda1775 | 294 | RVCT_ASM_EXPORT ArmReadIdPfr1\r |
bd6b9799 | 295 | mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r |
296 | bx lr\r | |
297 | \r | |
298 | END\r |