[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm

//------------------------------------------------------------------------------ \r
//\r
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
// Copyright (c) 2011, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution.  The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//------------------------------------------------------------------------------\r
\r
    EXPORT  ArmInvalidateInstructionCache\r
    EXPORT  ArmInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmCleanDataCacheEntryByMVA\r
    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA\r
    EXPORT  ArmInvalidateDataCacheEntryBySetWay\r
    EXPORT  ArmCleanDataCacheEntryBySetWay\r
    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay\r
    EXPORT  ArmDrainWriteBuffer\r
    EXPORT  ArmEnableMmu\r
    EXPORT  ArmDisableMmu\r
    EXPORT  ArmDisableCachesAndMmu\r
    EXPORT  ArmMmuEnabled\r
    EXPORT  ArmEnableDataCache\r
    EXPORT  ArmDisableDataCache\r
    EXPORT  ArmEnableInstructionCache\r
    EXPORT  ArmDisableInstructionCache\r
    EXPORT  ArmEnableSWPInstruction\r
    EXPORT  ArmEnableBranchPrediction\r
    EXPORT  ArmDisableBranchPrediction\r
    EXPORT  ArmSetLowVectors\r
    EXPORT  ArmSetHighVectors\r
    EXPORT  ArmV7AllDataCachesOperation\r
    EXPORT  ArmDataMemoryBarrier\r
    EXPORT  ArmDataSyncronizationBarrier\r
    EXPORT  ArmInstructionSynchronizationBarrier\r
    EXPORT  ArmWriteVBar\r
    EXPORT  ArmEnableVFP\r
    EXPORT  ArmCallWFI\r
    EXPORT  ArmReadCbar\r
    EXPORT  ArmInvalidateInstructionAndDataTlb\r
    EXPORT  ArmReadMpidr\r
    EXPORT  ArmReadTpidrurw\r
    EXPORT  ArmWriteTpidrurw\r
    EXPORT  ArmIsArchTimerImplemented\r
    EXPORT  ArmReadIdPfr1\r
\r
    AREA    ArmV7Support, CODE, READONLY\r
    PRESERVE8\r
\r
DC_ON           EQU     ( 0x1:SHL:2 )\r
IC_ON           EQU     ( 0x1:SHL:12 )\r
CTRL_M_BIT      EQU     (1 << 0)\r
CTRL_C_BIT      EQU     (1 << 2)\r
CTRL_B_BIT      EQU     (1 << 7)\r
CTRL_I_BIT      EQU     (1 << 12)\r
\r
\r
ArmInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line       \r
  dsb\r
  isb\r
  bx      lr\r
\r
ArmCleanDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     \r
  dsb\r
  isb\r
  bx      lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryByMVA\r
  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
  dsb\r
  isb\r
  bx      lr\r
\r
\r
ArmInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line    \r
  dsb\r
  isb\r
  bx      lr\r
\r
\r
ArmCleanInvalidateDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line    \r
  dsb\r
  isb\r
  bx      lr\r
\r
\r
ArmCleanDataCacheEntryBySetWay\r
  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line    \r
  dsb\r
  isb\r
  bx      lr\r
\r
\r
ArmInvalidateInstructionCache\r
  mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache\r
  isb\r
  bx      LR\r
\r
ArmEnableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableMmu\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
\r
  mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB\r
  mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableCachesAndMmu\r
  mrc   p15, 0, r0, c1, c0, 0           ; Get control register\r
  bic   r0, r0, #CTRL_M_BIT             ; Disable MMU\r
  bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache\r
  bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache\r
  mcr   p15, 0, r0, c1, c0, 0           ; Write control register\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmMmuEnabled\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  and     R0,R0,#1\r
  bx      LR\r
\r
ArmEnableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
    \r
ArmDisableDataCache\r
  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmEnableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
  \r
ArmDisableInstructionCache\r
  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit\r
  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)\r
  BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled\r
  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmEnableSWPInstruction\r
  mrc     p15, 0, r0, c1, c0, 0\r
  orr     r0, r0, #0x00000400\r
  mcr     p15, 0, r0, c1, c0, 0\r
  isb\r
  bx      LR\r
\r
ArmEnableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmDisableBranchPrediction\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00000800   ;\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  dsb\r
  isb\r
  bx      LR\r
\r
ArmSetLowVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmSetHighVectors\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  orr     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      LR\r
\r
ArmV7AllDataCachesOperation\r
  stmfd SP!,{r4-r12, LR}\r
  mov   R1, R0                ; Save Function call in R1\r
  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
  ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)\r
  mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)\r
  beq   Finished\r
  mov   R10, #0\r
\r
Loop1   \r
  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel\r
  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level\r
  and   R12, R12, #7            ; get those 3 bits alone\r
  cmp   R12, #2\r
  blt   Skip                    ; no cache or only instruction cache at this level\r
  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
  isb                           ; isb to sync the change to the CacheSizeID reg \r
  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)\r
  and   R2, R12, #&7            ; extract the line length field\r
  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)\r
  ldr   R4, =0x3FF\r
  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)\r
  clz   R5, R4                  ; R5 is the bit position of the way size increment\r
  ldr   R7, =0x00007FFF\r
  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)\r
\r
Loop2   \r
  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)\r
\r
Loop3   \r
  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11\r
  orr   R0, R0, R7, LSL R2      ; factor in the index number\r
\r
  blx   R1\r
\r
  subs  R9, R9, #1              ; decrement the way number\r
  bge   Loop3\r
  subs  R7, R7, #1              ; decrement the index\r
  bge   Loop2\r
Skip  \r
  add   R10, R10, #2            ; increment the cache number\r
  cmp   R3, R10\r
  bgt   Loop1\r
  \r
Finished\r
  dsb\r
  ldmfd SP!, {r4-r12, lr}\r
  bx    LR\r
\r
ArmDataMemoryBarrier\r
  dmb\r
  bx      LR\r
  \r
ArmDataSyncronizationBarrier\r
ArmDrainWriteBuffer\r
  dsb\r
  bx      LR\r
  \r
ArmInstructionSynchronizationBarrier\r
  isb\r
  bx      LR\r
\r
ArmWriteVBar\r
  // Set the Address of the Vector Table in the VBAR register\r
  mcr     p15, 0, r0, c12, c0, 0 \r
  // Ensure the SCTLR.V bit is clear\r
  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
  bic     r0, r0, #0x00002000   ; clear V bit\r
  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
  isb\r
  bx      lr\r
\r
ArmEnableVFP\r
  // Read CPACR (Coprocessor Access Control Register)\r
  mrc     p15, 0, r0, c1, c0, 2\r
  // Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
  orr     r0, r0, #0x00f00000\r
  // Write back CPACR (Coprocessor Access Control Register)\r
  mcr     p15, 0, r0, c1, c0, 2\r
  // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
  mov     r0, #0x40000000\r
  mcr     p10,#0x7,r0,c8,c0,#0\r
  bx      lr\r
\r
ArmCallWFI\r
  wfi\r
  bx      lr\r
\r
//Note: Return 0 in Uniprocessor implementation\r
ArmReadCbar\r
  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register\r
  bx      lr\r
\r
ArmInvalidateInstructionAndDataTlb\r
  mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB\r
  dsb\r
  bx lr\r
\r
ArmReadMpidr\r
  mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR\r
  bx      lr\r
\r
ArmReadTpidrurw\r
  mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW\r
  bx      lr\r
\r
ArmWriteTpidrurw\r
  mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW\r
  bx      lr\r
\r
ArmIsArchTimerImplemented\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1\r
  and    r0, r0, #0x000F0000\r
  bx     lr\r
\r
ArmReadIdPfr1\r
  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register\r
  bx     lr\r
\r
 END\r
Commit	Line	Data
bd6b9799	1	//------------------------------------------------------------------------------ \r
	2	//\r
	3	// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
	4	// Copyright (c) 2011, ARM Limited. All rights reserved.\r
	5	//\r
	6	// This program and the accompanying materials\r
	7	// are licensed and made available under the terms and conditions of the BSD License\r
	8	// which accompanies this distribution. The full text of the license may be found at\r
	9	// http://opensource.org/licenses/bsd-license.php\r
	10	//\r
	11	// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	//\r
	14	//------------------------------------------------------------------------------\r
	15	\r
	16	EXPORT ArmInvalidateInstructionCache\r
	17	EXPORT ArmInvalidateDataCacheEntryByMVA\r
	18	EXPORT ArmCleanDataCacheEntryByMVA\r
	19	EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
	20	EXPORT ArmInvalidateDataCacheEntryBySetWay\r
	21	EXPORT ArmCleanDataCacheEntryBySetWay\r
	22	EXPORT ArmCleanInvalidateDataCacheEntryBySetWay\r
	23	EXPORT ArmDrainWriteBuffer\r
	24	EXPORT ArmEnableMmu\r
	25	EXPORT ArmDisableMmu\r
	26	EXPORT ArmDisableCachesAndMmu\r
	27	EXPORT ArmMmuEnabled\r
	28	EXPORT ArmEnableDataCache\r
	29	EXPORT ArmDisableDataCache\r
	30	EXPORT ArmEnableInstructionCache\r
	31	EXPORT ArmDisableInstructionCache\r
	32	EXPORT ArmEnableSWPInstruction\r
	33	EXPORT ArmEnableBranchPrediction\r
	34	EXPORT ArmDisableBranchPrediction\r
	35	EXPORT ArmSetLowVectors\r
	36	EXPORT ArmSetHighVectors\r
	37	EXPORT ArmV7AllDataCachesOperation\r
	38	EXPORT ArmDataMemoryBarrier\r
	39	EXPORT ArmDataSyncronizationBarrier\r
	40	EXPORT ArmInstructionSynchronizationBarrier\r
	41	EXPORT ArmWriteVBar\r
	42	EXPORT ArmEnableVFP\r
	43	EXPORT ArmCallWFI\r
	44	EXPORT ArmReadCbar\r
	45	EXPORT ArmInvalidateInstructionAndDataTlb\r
	46	EXPORT ArmReadMpidr\r
	47	EXPORT ArmReadTpidrurw\r
	48	EXPORT ArmWriteTpidrurw\r
	49	EXPORT ArmIsArchTimerImplemented\r
	50	EXPORT ArmReadIdPfr1\r
	51	\r
	52	AREA ArmV7Support, CODE, READONLY\r
	53	PRESERVE8\r
	54	\r
	55	DC_ON EQU ( 0x1:SHL:2 )\r
	56	IC_ON EQU ( 0x1:SHL:12 )\r
	57	CTRL_M_BIT EQU (1 << 0)\r
	58	CTRL_C_BIT EQU (1 << 2)\r
	59	CTRL_B_BIT EQU (1 << 7)\r
	60	CTRL_I_BIT EQU (1 << 12)\r
	61	\r
	62	\r
	63	ArmInvalidateDataCacheEntryByMVA\r
	64	mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line \r
65	dsb\r
66	isb\r
67	bx lr\r
68	\r
69	ArmCleanDataCacheEntryByMVA\r
70	mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line \r
71	dsb\r
72	isb\r
73	bx lr\r
74	\r
75	\r
76	ArmCleanInvalidateDataCacheEntryByMVA\r
77	mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
78	dsb\r
79	isb\r
80	bx lr\r
81	\r
82	\r
83	ArmInvalidateDataCacheEntryBySetWay\r
84	mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line \r
85	dsb\r
86	isb\r
87	bx lr\r
88	\r
89	\r
90	ArmCleanInvalidateDataCacheEntryBySetWay\r
91	mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line \r
92	dsb\r
93	isb\r
94	bx lr\r
95	\r
96	\r
97	ArmCleanDataCacheEntryBySetWay\r
98	mcr p15, 0, r0, c7, c10, 2 ; Clean this line \r
99	dsb\r
100	isb\r
101	bx lr\r
102	\r
103	\r
104	ArmInvalidateInstructionCache\r
105	mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
106	isb\r
107	bx LR\r
108	\r
109	ArmEnableMmu\r
110	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
111	orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU\r
112	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
113	dsb\r
114	isb\r
115	bx LR\r
116	\r
117	ArmDisableMmu\r
118	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
119	bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU\r
120	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
121	\r
122	mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB\r
123	mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array\r
124	dsb\r
125	isb\r
126	bx LR\r
127	\r
128	ArmDisableCachesAndMmu\r
129	mrc p15, 0, r0, c1, c0, 0 ; Get control register\r
130	bic r0, r0, #CTRL_M_BIT ; Disable MMU\r
131	bic r0, r0, #CTRL_C_BIT ; Disable D Cache\r
132	bic r0, r0, #CTRL_I_BIT ; Disable I Cache\r
133	mcr p15, 0, r0, c1, c0, 0 ; Write control register\r
134	dsb\r
135	isb\r
136	bx LR\r
137	\r
138	ArmMmuEnabled\r
139	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
140	and R0,R0,#1\r
141	bx LR\r
142	\r
143	ArmEnableDataCache\r
144	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
145	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
146	orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled\r
147	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
148	dsb\r
149	isb\r
150	bx LR\r
151	\r
152	ArmDisableDataCache\r
153	ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit\r
154	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
155	bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled\r
156	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
157	dsb\r
158	isb\r
159	bx LR\r
160	\r
161	ArmEnableInstructionCache\r
162	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
163	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
164	orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled\r
165	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
166	dsb\r
167	isb\r
168	bx LR\r
169	\r
170	ArmDisableInstructionCache\r
171	ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit\r
172	mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)\r
173	BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled\r
174	mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)\r
175	isb\r
176	bx LR\r
177	\r
178	ArmEnableSWPInstruction\r
179	mrc p15, 0, r0, c1, c0, 0\r
180	orr r0, r0, #0x00000400\r
181	mcr p15, 0, r0, c1, c0, 0\r
182	isb\r
183	bx LR\r
184	\r
185	ArmEnableBranchPrediction\r
186	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
187	orr r0, r0, #0x00000800 ;\r
188	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
189	dsb\r
190	isb\r
191	bx LR\r
192	\r
193	ArmDisableBranchPrediction\r
194	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
195	bic r0, r0, #0x00000800 ;\r
196	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
197	dsb\r
198	isb\r
199	bx LR\r
200	\r
201	ArmSetLowVectors\r
202	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
203	bic r0, r0, #0x00002000 ; clear V bit\r
204	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
205	isb\r
206	bx LR\r
207	\r
208	ArmSetHighVectors\r
209	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
210	orr r0, r0, #0x00002000 ; clear V bit\r
211	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
212	isb\r
213	bx LR\r
214	\r
215	ArmV7AllDataCachesOperation\r
216	stmfd SP!,{r4-r12, LR}\r
217	mov R1, R0 ; Save Function call in R1\r
218	mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR\r
219	ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)\r
220	mov R3, R3, LSR #23 ; Cache level value (naturally aligned)\r
221	beq Finished\r
222	mov R10, #0\r
223	\r
224	Loop1 \r
225	add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
226	mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
227	and R12, R12, #7 ; get those 3 bits alone\r
228	cmp R12, #2\r
229	blt Skip ; no cache or only instruction cache at this level\r
230	mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
231	isb ; isb to sync the change to the CacheSizeID reg \r
232	mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)\r
233	and R2, R12, #&7 ; extract the line length field\r
234	add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)\r
235	ldr R4, =0x3FF\r
236	ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)\r
237	clz R5, R4 ; R5 is the bit position of the way size increment\r
238	ldr R7, =0x00007FFF\r
239	ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)\r
240	\r
241	Loop2 \r
242	mov R9, R4 ; R9 working copy of the max way size (right aligned)\r
243	\r
244	Loop3 \r
245	orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11\r
246	orr R0, R0, R7, LSL R2 ; factor in the index number\r
247	\r
248	blx R1\r
249	\r
250	subs R9, R9, #1 ; decrement the way number\r
251	bge Loop3\r
252	subs R7, R7, #1 ; decrement the index\r
253	bge Loop2\r
254	Skip \r
255	add R10, R10, #2 ; increment the cache number\r
256	cmp R3, R10\r
257	bgt Loop1\r
258	\r
259	Finished\r
260	dsb\r
261	ldmfd SP!, {r4-r12, lr}\r
262	bx LR\r
263	\r
264	ArmDataMemoryBarrier\r
265	dmb\r
266	bx LR\r
267	\r
268	ArmDataSyncronizationBarrier\r
269	ArmDrainWriteBuffer\r
270	dsb\r
271	bx LR\r
272	\r
273	ArmInstructionSynchronizationBarrier\r
274	isb\r
275	bx LR\r
276	\r
277	ArmWriteVBar\r
278	// Set the Address of the Vector Table in the VBAR register\r
279	mcr p15, 0, r0, c12, c0, 0 \r
280	// Ensure the SCTLR.V bit is clear\r
281	mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)\r
282	bic r0, r0, #0x00002000 ; clear V bit\r
283	mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)\r
284	isb\r
285	bx lr\r
286	\r
287	ArmEnableVFP\r
288	// Read CPACR (Coprocessor Access Control Register)\r
289	mrc p15, 0, r0, c1, c0, 2\r
290	// Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
291	orr r0, r0, #0x00f00000\r
292	// Write back CPACR (Coprocessor Access Control Register)\r
293	mcr p15, 0, r0, c1, c0, 2\r
294	// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
295	mov r0, #0x40000000\r
296	mcr p10,#0x7,r0,c8,c0,#0\r
297	bx lr\r
298	\r
299	ArmCallWFI\r
300	wfi\r
301	bx lr\r
302	\r
303	//Note: Return 0 in Uniprocessor implementation\r
304	ArmReadCbar\r
305	mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register\r
306	bx lr\r
307	\r
308	ArmInvalidateInstructionAndDataTlb\r
309	mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB\r
310	dsb\r
311	bx lr\r
312	\r
313	ArmReadMpidr\r
314	mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
315	bx lr\r
316	\r
317	ArmReadTpidrurw\r
318	mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
319	bx lr\r
320	\r
321	ArmWriteTpidrurw\r
322	mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW\r
323	bx lr\r
324	\r
325	ArmIsArchTimerImplemented\r
326	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1\r
327	and r0, r0, #0x000F0000\r
328	bx lr\r
329	\r
330	ArmReadIdPfr1\r
331	mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register\r
332	bx lr\r
333	\r
334	END\r