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3402aac7 | 1 | #------------------------------------------------------------------------------\r |
bd6b9799 | 2 | #\r |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
ff1f27c0 | 4 | # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | #\r |
6 | # This program and the accompanying materials\r | |
7 | # are licensed and made available under the terms and conditions of the BSD License\r | |
8 | # which accompanies this distribution. The full text of the license may be found at\r | |
9 | # http://opensource.org/licenses/bsd-license.php\r | |
10 | #\r | |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | #\r | |
14 | #------------------------------------------------------------------------------\r | |
15 | \r | |
16 | #include <AsmMacroIoLib.h>\r | |
17 | \r | |
bd6b9799 | 18 | .text\r |
19 | .align 2\r | |
f6c5a29b | 20 | GCC_ASM_EXPORT(ArmReadMidr)\r |
64751727 | 21 | GCC_ASM_EXPORT(ArmCacheInfo)\r |
bd6b9799 | 22 | GCC_ASM_EXPORT(ArmGetInterruptState)\r |
23 | GCC_ASM_EXPORT(ArmGetFiqState)\r | |
24 | GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r | |
25 | GCC_ASM_EXPORT(ArmSetTTBR0)\r | |
ff1f27c0 | 26 | GCC_ASM_EXPORT(ArmSetTTBCR)\r |
bd6b9799 | 27 | GCC_ASM_EXPORT(ArmSetDomainAccessControl)\r |
28 | GCC_ASM_EXPORT(CPSRMaskInsert)\r | |
29 | GCC_ASM_EXPORT(CPSRRead)\r | |
836c3500 | 30 | GCC_ASM_EXPORT(ArmReadCpacr)\r |
31 | GCC_ASM_EXPORT(ArmWriteCpacr)\r | |
bd6b9799 | 32 | GCC_ASM_EXPORT(ArmWriteAuxCr)\r |
33 | GCC_ASM_EXPORT(ArmReadAuxCr)\r | |
34 | GCC_ASM_EXPORT(ArmInvalidateTlb)\r | |
35 | GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r | |
836c3500 | 36 | GCC_ASM_EXPORT(ArmReadScr)\r |
bd6b9799 | 37 | GCC_ASM_EXPORT(ArmWriteScr)\r |
836c3500 | 38 | GCC_ASM_EXPORT(ArmReadMVBar)\r |
39 | GCC_ASM_EXPORT(ArmWriteMVBar)\r | |
5ea2c2d3 | 40 | GCC_ASM_EXPORT(ArmReadHVBar)\r |
41 | GCC_ASM_EXPORT(ArmWriteHVBar)\r | |
b1d41be7 | 42 | GCC_ASM_EXPORT(ArmCallWFE)\r |
43 | GCC_ASM_EXPORT(ArmCallSEV)\r | |
836c3500 | 44 | GCC_ASM_EXPORT(ArmReadSctlr)\r |
52d44f77 OM |
45 | GCC_ASM_EXPORT(ArmReadCpuActlr)\r |
46 | GCC_ASM_EXPORT(ArmWriteCpuActlr)\r | |
bd6b9799 | 47 | \r |
48 | #------------------------------------------------------------------------------\r | |
49 | \r | |
f6c5a29b | 50 | ASM_PFX(ArmReadMidr):\r |
bd6b9799 | 51 | mrc p15,0,R0,c0,c0,0\r |
52 | bx LR\r | |
53 | \r | |
64751727 | 54 | ASM_PFX(ArmCacheInfo):\r |
bd6b9799 | 55 | mrc p15,0,R0,c0,c0,1\r |
56 | bx LR\r | |
57 | \r | |
58 | ASM_PFX(ArmGetInterruptState):\r | |
59 | mrs R0,CPSR\r | |
60 | tst R0,#0x80 @Check if IRQ is enabled.\r | |
61 | moveq R0,#1\r | |
62 | movne R0,#0\r | |
63 | bx LR\r | |
64 | \r | |
65 | ASM_PFX(ArmGetFiqState):\r | |
66 | mrs R0,CPSR\r | |
67 | tst R0,#0x40 @Check if FIQ is enabled.\r | |
68 | moveq R0,#1\r | |
69 | movne R0,#0\r | |
70 | bx LR\r | |
71 | \r | |
72 | ASM_PFX(ArmSetDomainAccessControl):\r | |
73 | mcr p15,0,r0,c3,c0,0\r | |
74 | bx lr\r | |
75 | \r | |
76 | ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert\r | |
77 | stmfd sp!, {r4-r12, lr} @ save all the banked registers\r | |
78 | mov r3, sp @ copy the stack pointer into a non-banked register\r | |
79 | mrs r2, cpsr @ read the cpsr\r | |
80 | bic r2, r2, r0 @ clear mask in the cpsr\r | |
81 | and r1, r1, r0 @ clear bits outside the mask in the input\r | |
82 | orr r2, r2, r1 @ set field\r | |
83 | msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r | |
84 | isb\r | |
85 | mov sp, r3 @ restore stack pointer\r | |
86 | ldmfd sp!, {r4-r12, lr} @ restore registers\r | |
27995cd5 | 87 | bx lr @ return (hopefully thumb-safe!)\r |
bd6b9799 | 88 | \r |
89 | ASM_PFX(CPSRRead):\r | |
90 | mrs r0, cpsr\r | |
91 | bx lr\r | |
92 | \r | |
836c3500 | 93 | ASM_PFX(ArmReadCpacr):\r |
94 | mrc p15, 0, r0, c1, c0, 2\r | |
95 | bx lr\r | |
96 | \r | |
97 | ASM_PFX(ArmWriteCpacr):\r | |
bd6b9799 | 98 | mcr p15, 0, r0, c1, c0, 2\r |
18029bb9 | 99 | isb\r |
bd6b9799 | 100 | bx lr\r |
101 | \r | |
102 | ASM_PFX(ArmWriteAuxCr):\r | |
103 | mcr p15, 0, r0, c1, c0, 1\r | |
104 | bx lr\r | |
105 | \r | |
106 | ASM_PFX(ArmReadAuxCr):\r | |
107 | mrc p15, 0, r0, c1, c0, 1\r | |
3402aac7 | 108 | bx lr\r |
bd6b9799 | 109 | \r |
110 | ASM_PFX(ArmSetTTBR0):\r | |
111 | mcr p15,0,r0,c2,c0,0\r | |
112 | isb\r | |
113 | bx lr\r | |
114 | \r | |
ff1f27c0 EL |
115 | ASM_PFX(ArmSetTTBCR):\r |
116 | mcr p15, 0, r0, c2, c0, 2\r | |
117 | isb\r | |
118 | bx lr\r | |
119 | \r | |
bd6b9799 | 120 | ASM_PFX(ArmGetTTBR0BaseAddress):\r |
121 | mrc p15,0,r0,c2,c0,0\r | |
122 | LoadConstantToReg(0xFFFFC000, r1)\r | |
123 | and r0, r0, r1\r | |
124 | isb\r | |
125 | bx lr\r | |
126 | \r | |
127 | //\r | |
128 | //VOID\r | |
129 | //ArmUpdateTranslationTableEntry (\r | |
130 | // IN VOID *TranslationTableEntry // R0\r | |
131 | // IN VOID *MVA // R1\r | |
132 | // );\r | |
133 | ASM_PFX(ArmUpdateTranslationTableEntry):\r | |
134 | mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA\r | |
135 | dsb\r | |
3402aac7 | 136 | mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA\r |
bd6b9799 | 137 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r |
138 | dsb\r | |
139 | isb\r | |
140 | bx lr\r | |
141 | \r | |
142 | ASM_PFX(ArmInvalidateTlb):\r | |
143 | mov r0,#0\r | |
144 | mcr p15,0,r0,c8,c7,0\r | |
145 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
146 | dsb\r | |
147 | isb\r | |
148 | bx lr\r | |
149 | \r | |
836c3500 | 150 | ASM_PFX(ArmReadScr):\r |
151 | mrc p15, 0, r0, c1, c1, 0\r | |
152 | bx lr\r | |
153 | \r | |
bd6b9799 | 154 | ASM_PFX(ArmWriteScr):\r |
155 | mcr p15, 0, r0, c1, c1, 0\r | |
b2d0e0c5 | 156 | isb\r |
bd6b9799 | 157 | bx lr\r |
158 | \r | |
5ea2c2d3 | 159 | ASM_PFX(ArmReadHVBar):\r |
160 | mrc p15, 4, r0, c12, c0, 0\r | |
161 | bx lr\r | |
162 | \r | |
163 | ASM_PFX(ArmWriteHVBar):\r | |
164 | mcr p15, 4, r0, c12, c0, 0\r | |
165 | bx lr\r | |
166 | \r | |
836c3500 | 167 | ASM_PFX(ArmReadMVBar):\r |
168 | mrc p15, 0, r0, c12, c0, 1\r | |
169 | bx lr\r | |
170 | \r | |
171 | ASM_PFX(ArmWriteMVBar):\r | |
bd6b9799 | 172 | mcr p15, 0, r0, c12, c0, 1\r |
173 | bx lr\r | |
174 | \r | |
b1d41be7 | 175 | ASM_PFX(ArmCallWFE):\r |
176 | wfe\r | |
177 | bx lr\r | |
178 | \r | |
179 | ASM_PFX(ArmCallSEV):\r | |
180 | sev\r | |
181 | bx lr\r | |
182 | \r | |
836c3500 | 183 | ASM_PFX(ArmReadSctlr):\r |
52d44f77 OM |
184 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r |
185 | bx lr\r | |
186 | \r | |
187 | ASM_PFX(ArmReadCpuActlr):\r | |
188 | mrc p15, 0, r0, c1, c0, 1\r | |
189 | bx lr\r | |
190 | \r | |
191 | ASM_PFX(ArmWriteCpuActlr):\r | |
192 | mcr p15, 0, r0, c1, c0, 1\r | |
193 | dsb\r | |
194 | isb\r | |
195 | bx lr\r | |
836c3500 | 196 | \r |
bd6b9799 | 197 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |