Commit | Line | Data |
---|---|---|
3402aac7 | 1 | //------------------------------------------------------------------------------\r |
bd6b9799 | 2 | //\r |
3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
f6c5a29b | 4 | // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
bd6b9799 | 5 | //\r |
6 | // This program and the accompanying materials\r | |
7 | // are licensed and made available under the terms and conditions of the BSD License\r | |
8 | // which accompanies this distribution. The full text of the license may be found at\r | |
9 | // http://opensource.org/licenses/bsd-license.php\r | |
10 | //\r | |
11 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | //\r | |
14 | //------------------------------------------------------------------------------\r | |
15 | \r | |
16 | #include <AsmMacroIoLib.h>\r | |
3402aac7 | 17 | \r |
bd6b9799 | 18 | INCLUDE AsmMacroIoLib.inc\r |
19 | \r | |
efda1775 EC |
20 | \r |
21 | INCLUDE AsmMacroExport.inc\r | |
22 | \r | |
23 | RVCT_ASM_EXPORT ArmReadMidr\r | |
bd6b9799 | 24 | mrc p15,0,R0,c0,c0,0\r |
25 | bx LR\r | |
26 | \r | |
efda1775 | 27 | RVCT_ASM_EXPORT ArmCacheInfo\r |
bd6b9799 | 28 | mrc p15,0,R0,c0,c0,1\r |
29 | bx LR\r | |
30 | \r | |
efda1775 | 31 | RVCT_ASM_EXPORT ArmGetInterruptState\r |
bd6b9799 | 32 | mrs R0,CPSR\r |
33 | tst R0,#0x80 // Check if IRQ is enabled.\r | |
34 | moveq R0,#1\r | |
35 | movne R0,#0\r | |
36 | bx LR\r | |
37 | \r | |
efda1775 | 38 | RVCT_ASM_EXPORT ArmGetFiqState\r |
bd6b9799 | 39 | mrs R0,CPSR\r |
40 | tst R0,#0x40 // Check if FIQ is enabled.\r | |
41 | moveq R0,#1\r | |
42 | movne R0,#0\r | |
43 | bx LR\r | |
44 | \r | |
efda1775 | 45 | RVCT_ASM_EXPORT ArmSetDomainAccessControl\r |
bd6b9799 | 46 | mcr p15,0,r0,c3,c0,0\r |
47 | bx lr\r | |
48 | \r | |
efda1775 | 49 | RVCT_ASM_EXPORT CPSRMaskInsert\r |
bd6b9799 | 50 | stmfd sp!, {r4-r12, lr} // save all the banked registers\r |
51 | mov r3, sp // copy the stack pointer into a non-banked register\r | |
52 | mrs r2, cpsr // read the cpsr\r | |
53 | bic r2, r2, r0 // clear mask in the cpsr\r | |
54 | and r1, r1, r0 // clear bits outside the mask in the input\r | |
55 | orr r2, r2, r1 // set field\r | |
56 | msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)\r | |
57 | isb\r | |
58 | mov sp, r3 // restore stack pointer\r | |
59 | ldmfd sp!, {r4-r12, lr} // restore registers\r | |
60 | bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)\r | |
61 | \r | |
efda1775 | 62 | RVCT_ASM_EXPORT CPSRRead\r |
bd6b9799 | 63 | mrs r0, cpsr\r |
64 | bx lr\r | |
65 | \r | |
efda1775 | 66 | RVCT_ASM_EXPORT ArmReadCpacr\r |
836c3500 | 67 | mrc p15, 0, r0, c1, c0, 2\r |
68 | bx lr\r | |
69 | \r | |
efda1775 | 70 | RVCT_ASM_EXPORT ArmWriteCpacr\r |
bd6b9799 | 71 | mcr p15, 0, r0, c1, c0, 2\r |
18029bb9 | 72 | isb\r |
bd6b9799 | 73 | bx lr\r |
74 | \r | |
efda1775 | 75 | RVCT_ASM_EXPORT ArmWriteAuxCr\r |
bd6b9799 | 76 | mcr p15, 0, r0, c1, c0, 1\r |
77 | bx lr\r | |
78 | \r | |
efda1775 | 79 | RVCT_ASM_EXPORT ArmReadAuxCr\r |
bd6b9799 | 80 | mrc p15, 0, r0, c1, c0, 1\r |
3402aac7 | 81 | bx lr\r |
bd6b9799 | 82 | \r |
efda1775 | 83 | RVCT_ASM_EXPORT ArmSetTTBR0\r |
bd6b9799 | 84 | mcr p15,0,r0,c2,c0,0\r |
85 | isb\r | |
86 | bx lr\r | |
87 | \r | |
efda1775 | 88 | RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress\r |
bd6b9799 | 89 | mrc p15,0,r0,c2,c0,0\r |
90 | LoadConstantToReg(0xFFFFC000, r1)\r | |
91 | and r0, r0, r1\r | |
92 | isb\r | |
93 | bx lr\r | |
94 | \r | |
95 | //\r | |
96 | //VOID\r | |
97 | //ArmUpdateTranslationTableEntry (\r | |
98 | // IN VOID *TranslationTableEntry // R0\r | |
99 | // IN VOID *MVA // R1\r | |
100 | // );\r | |
efda1775 | 101 | RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry\r |
bd6b9799 | 102 | mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA\r |
103 | dsb\r | |
104 | mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA\r | |
105 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
106 | dsb\r | |
107 | isb\r | |
108 | bx lr\r | |
109 | \r | |
efda1775 | 110 | RVCT_ASM_EXPORT ArmInvalidateTlb\r |
bd6b9799 | 111 | mov r0,#0\r |
112 | mcr p15,0,r0,c8,c7,0\r | |
113 | mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp\r | |
114 | dsb\r | |
115 | isb\r | |
116 | bx lr\r | |
117 | \r | |
efda1775 | 118 | RVCT_ASM_EXPORT ArmReadScr\r |
836c3500 | 119 | mrc p15, 0, r0, c1, c1, 0\r |
120 | bx lr\r | |
121 | \r | |
efda1775 | 122 | RVCT_ASM_EXPORT ArmWriteScr\r |
bd6b9799 | 123 | mcr p15, 0, r0, c1, c1, 0\r |
124 | bx lr\r | |
125 | \r | |
efda1775 | 126 | RVCT_ASM_EXPORT ArmReadHVBar\r |
5ea2c2d3 | 127 | mrc p15, 4, r0, c12, c0, 0\r |
128 | bx lr\r | |
129 | \r | |
efda1775 | 130 | RVCT_ASM_EXPORT ArmWriteHVBar\r |
5ea2c2d3 | 131 | mcr p15, 4, r0, c12, c0, 0\r |
132 | bx lr\r | |
133 | \r | |
efda1775 | 134 | RVCT_ASM_EXPORT ArmReadMVBar\r |
836c3500 | 135 | mrc p15, 0, r0, c12, c0, 1\r |
136 | bx lr\r | |
137 | \r | |
efda1775 | 138 | RVCT_ASM_EXPORT ArmWriteMVBar\r |
bd6b9799 | 139 | mcr p15, 0, r0, c12, c0, 1\r |
140 | bx lr\r | |
3402aac7 | 141 | \r |
efda1775 | 142 | RVCT_ASM_EXPORT ArmCallWFE\r |
b1d41be7 | 143 | wfe\r |
27995cd5 | 144 | bx lr\r |
b1d41be7 | 145 | \r |
efda1775 | 146 | RVCT_ASM_EXPORT ArmCallSEV\r |
b1d41be7 | 147 | sev\r |
27995cd5 | 148 | bx lr\r |
b1d41be7 | 149 | \r |
efda1775 | 150 | RVCT_ASM_EXPORT ArmReadSctlr\r |
27995cd5 | 151 | mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)\r |
91c38d4e | 152 | bx lr\r |
52d44f77 OM |
153 | \r |
154 | \r | |
efda1775 | 155 | RVCT_ASM_EXPORT ArmReadCpuActlr\r |
52d44f77 OM |
156 | mrc p15, 0, r0, c1, c0, 1\r |
157 | bx lr\r | |
158 | \r | |
efda1775 | 159 | RVCT_ASM_EXPORT ArmWriteCpuActlr\r |
52d44f77 OM |
160 | mcr p15, 0, r0, c1, c0, 1\r |
161 | dsb\r | |
162 | isb\r | |
163 | bx lr\r | |
836c3500 | 164 | \r |
bd6b9799 | 165 | END\r |