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1 | #------------------------------------------------------------------------------ \r |
2 | #\r |
3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
4 | # Copyright (c) 2011, ARM Limited. All rights reserved.\r |
5 | #\r |
6 | # This program and the accompanying materials\r |
7 | # are licensed and made available under the terms and conditions of the BSD License\r |
8 | # which accompanies this distribution. The full text of the license may be found at\r |
9 | # http://opensource.org/licenses/bsd-license.php\r |
10 | #\r |
11 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
12 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
13 | #\r |
14 | #------------------------------------------------------------------------------\r |
15 | \r |
16 | #include <AsmMacroIoLib.h>\r |
17 | \r |
18 | #ifdef ARM_CPU_ARMv6\r |
19 | // No memory barriers for ARMv6\r |
20 | #define isb\r |
21 | #define dsb\r |
22 | #endif\r |
23 | \r |
24 | .text\r |
25 | .align 2\r |
26 | GCC_ASM_EXPORT(Cp15IdCode)\r |
27 | GCC_ASM_EXPORT(Cp15CacheInfo)\r |
28 | GCC_ASM_EXPORT(ArmGetInterruptState)\r |
29 | GCC_ASM_EXPORT(ArmGetFiqState)\r |
30 | GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)\r |
31 | GCC_ASM_EXPORT(ArmSetTTBR0)\r |
32 | GCC_ASM_EXPORT(ArmSetDomainAccessControl)\r |
33 | GCC_ASM_EXPORT(CPSRMaskInsert)\r |
34 | GCC_ASM_EXPORT(CPSRRead)\r |
35 | GCC_ASM_EXPORT(ArmWriteCPACR)\r |
36 | GCC_ASM_EXPORT(ArmWriteAuxCr)\r |
37 | GCC_ASM_EXPORT(ArmReadAuxCr)\r |
38 | GCC_ASM_EXPORT(ArmInvalidateTlb)\r |
39 | GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r |
40 | GCC_ASM_EXPORT(ArmWriteNsacr)\r |
41 | GCC_ASM_EXPORT(ArmWriteScr)\r |
42 | GCC_ASM_EXPORT(ArmWriteVMBar)\r |
43 | \r |
44 | #------------------------------------------------------------------------------\r |
45 | \r |
46 | ASM_PFX(Cp15IdCode):\r |
47 | mrc p15,0,R0,c0,c0,0\r |
48 | bx LR\r |
49 | \r |
50 | ASM_PFX(Cp15CacheInfo):\r |
51 | mrc p15,0,R0,c0,c0,1\r |
52 | bx LR\r |
53 | \r |
54 | ASM_PFX(ArmGetInterruptState):\r |
55 | mrs R0,CPSR\r |
56 | tst R0,#0x80 @Check if IRQ is enabled.\r |
57 | moveq R0,#1\r |
58 | movne R0,#0\r |
59 | bx LR\r |
60 | \r |
61 | ASM_PFX(ArmGetFiqState):\r |
62 | mrs R0,CPSR\r |
63 | tst R0,#0x40 @Check if FIQ is enabled.\r |
64 | moveq R0,#1\r |
65 | movne R0,#0\r |
66 | bx LR\r |
67 | \r |
68 | ASM_PFX(ArmSetDomainAccessControl):\r |
69 | mcr p15,0,r0,c3,c0,0\r |
70 | bx lr\r |
71 | \r |
72 | ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert\r |
73 | stmfd sp!, {r4-r12, lr} @ save all the banked registers\r |
74 | mov r3, sp @ copy the stack pointer into a non-banked register\r |
75 | mrs r2, cpsr @ read the cpsr\r |
76 | bic r2, r2, r0 @ clear mask in the cpsr\r |
77 | and r1, r1, r0 @ clear bits outside the mask in the input\r |
78 | orr r2, r2, r1 @ set field\r |
79 | msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)\r |
80 | isb\r |
81 | mov sp, r3 @ restore stack pointer\r |
82 | ldmfd sp!, {r4-r12, lr} @ restore registers\r |
83 | bx lr @ return (hopefully thumb-safe!) @ return (hopefully thumb-safe!)\r |
84 | \r |
85 | ASM_PFX(CPSRRead):\r |
86 | mrs r0, cpsr\r |
87 | bx lr\r |
88 | \r |
89 | ASM_PFX(ArmWriteCPACR):\r |
90 | mcr p15, 0, r0, c1, c0, 2\r |
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91 | isb\r |
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92 | bx lr\r |
93 | \r |
94 | ASM_PFX(ArmWriteAuxCr):\r |
95 | mcr p15, 0, r0, c1, c0, 1\r |
96 | bx lr\r |
97 | \r |
98 | ASM_PFX(ArmReadAuxCr):\r |
99 | mrc p15, 0, r0, c1, c0, 1\r |
100 | bx lr \r |
101 | \r |
102 | ASM_PFX(ArmSetTTBR0):\r |
103 | mcr p15,0,r0,c2,c0,0\r |
104 | isb\r |
105 | bx lr\r |
106 | \r |
107 | ASM_PFX(ArmGetTTBR0BaseAddress):\r |
108 | mrc p15,0,r0,c2,c0,0\r |
109 | LoadConstantToReg(0xFFFFC000, r1)\r |
110 | and r0, r0, r1\r |
111 | isb\r |
112 | bx lr\r |
113 | \r |
114 | //\r |
115 | //VOID\r |
116 | //ArmUpdateTranslationTableEntry (\r |
117 | // IN VOID *TranslationTableEntry // R0\r |
118 | // IN VOID *MVA // R1\r |
119 | // );\r |
120 | ASM_PFX(ArmUpdateTranslationTableEntry):\r |
121 | mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA\r |
122 | dsb\r |
123 | mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA \r |
124 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r |
125 | dsb\r |
126 | isb\r |
127 | bx lr\r |
128 | \r |
129 | ASM_PFX(ArmInvalidateTlb):\r |
130 | mov r0,#0\r |
131 | mcr p15,0,r0,c8,c7,0\r |
132 | mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp\r |
133 | dsb\r |
134 | isb\r |
135 | bx lr\r |
136 | \r |
137 | ASM_PFX(ArmWriteNsacr):\r |
138 | mcr p15, 0, r0, c1, c1, 2\r |
139 | bx lr\r |
140 | \r |
141 | ASM_PFX(ArmWriteScr):\r |
142 | mcr p15, 0, r0, c1, c1, 0\r |
143 | bx lr\r |
144 | \r |
145 | ASM_PFX(ArmWriteVMBar):\r |
146 | mcr p15, 0, r0, c12, c0, 1\r |
147 | bx lr\r |
148 | \r |
149 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |