projects / mirror_edk2.git / blame
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|---|---|---|
| 2ef2b01e A |
1 | //------------------------------------------------------------------------------ |
| 2 | // | |
| d6ebcab7 | 3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> |
| 2ef2b01e | 4 | // |
| d6ebcab7 | 5 | // This program and the accompanying materials |
| 2ef2b01e A |
6 | // are licensed and made available under the terms and conditions of the BSD License |
| 7 | // which accompanies this distribution. The full text of the license may be found at | |
| 8 | // http://opensource.org/licenses/bsd-license.php | |
| 9 | // | |
| 10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
| 11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
| 12 | // | |
| 13 | //------------------------------------------------------------------------------ | |
| 14 | ||
| 15 | ||
| 16 | EXPORT Cp15IdCode | |
| 17 | EXPORT Cp15CacheInfo | |
| 18 | EXPORT ArmEnableInterrupts | |
| 19 | EXPORT ArmDisableInterrupts | |
| 20 | EXPORT ArmGetInterruptState | |
| 0416278c | 21 | EXPORT ArmEnableFiq |
| 22 | EXPORT ArmDisableFiq | |
| 23 | EXPORT ArmGetFiqState | |
| 2ef2b01e A |
24 | EXPORT ArmInvalidateTlb |
| 25 | EXPORT ArmSetTranslationTableBaseAddress | |
| c2b5ca8b | 26 | EXPORT ArmGetTranslationTableBaseAddress |
| 2ef2b01e A |
27 | EXPORT ArmSetDomainAccessControl |
| 28 | EXPORT CPSRMaskInsert | |
| 29 | EXPORT CPSRRead | |
| 30 | ||
| 31 | AREA ArmLibSupport, CODE, READONLY | |
| 32 | ||
| 33 | Cp15IdCode | |
| 34 | mrc p15,0,R0,c0,c0,0 | |
| 35 | bx LR | |
| 36 | ||
| 37 | Cp15CacheInfo | |
| 38 | mrc p15,0,R0,c0,c0,1 | |
| 39 | bx LR | |
| 40 | ||
| 41 | ArmEnableInterrupts | |
| 42 | mrs R0,CPSR | |
| 43 | bic R0,R0,#0x80 ;Enable IRQ interrupts | |
| 44 | msr CPSR_c,R0 | |
| 45 | bx LR | |
| 46 | ||
| 47 | ArmDisableInterrupts | |
| 48 | mrs R0,CPSR | |
| 49 | orr R1,R0,#0x80 ;Disable IRQ interrupts | |
| 50 | msr CPSR_c,R1 | |
| 51 | tst R0,#0x80 | |
| 52 | moveq R0,#1 | |
| 53 | movne R0,#0 | |
| 54 | bx LR | |
| 55 | ||
| 56 | ArmGetInterruptState | |
| 57 | mrs R0,CPSR | |
| 58 | tst R0,#0x80 ;Check if IRQ is enabled. | |
| 59 | moveq R0,#1 | |
| 60 | movne R0,#0 | |
| 61 | bx LR | |
| 0416278c | 62 | |
| 63 | ArmEnableFiq | |
| 64 | mrs R0,CPSR | |
| 65 | bic R0,R0,#0x40 ;Enable IRQ interrupts | |
| 66 | msr CPSR_c,R0 | |
| 67 | bx LR | |
| 68 | ||
| 69 | ArmDisableFiq | |
| 70 | mrs R0,CPSR | |
| 71 | orr R1,R0,#0x40 ;Disable IRQ interrupts | |
| 72 | msr CPSR_c,R1 | |
| 73 | tst R0,#0x40 | |
| 74 | moveq R0,#1 | |
| 75 | movne R0,#0 | |
| 76 | bx LR | |
| 77 | ||
| 78 | ArmGetFiqState | |
| 79 | mrs R0,CPSR | |
| 80 | tst R0,#0x40 ;Check if IRQ is enabled. | |
| 81 | moveq R0,#1 | |
| 82 | movne R0,#0 | |
| 83 | bx LR | |
| 2ef2b01e A |
84 | |
| 85 | ArmInvalidateTlb | |
| 86 | mov r0,#0 | |
| 87 | mcr p15,0,r0,c8,c7,0 | |
| 88 | bx lr | |
| 89 | ||
| 90 | ArmSetTranslationTableBaseAddress | |
| 91 | mcr p15,0,r0,c2,c0,0 | |
| 92 | bx lr | |
| 93 | ||
| f659880b | 94 | ArmGetTranslationTableBaseAddress |
| c2b5ca8b A |
95 | mrc p15,0,r0,c2,c0,0 |
| 96 | bx lr | |
| 97 | ||
| 2ef2b01e A |
98 | ArmSetDomainAccessControl |
| 99 | mcr p15,0,r0,c3,c0,0 | |
| 100 | bx lr | |
| 101 | ||
| 102 | CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert | |
| 103 | stmfd sp!, {r4-r12, lr} ; save all the banked registers | |
| 104 | mov r3, sp ; copy the stack pointer into a non-banked register | |
| 105 | mrs r2, cpsr ; read the cpsr | |
| 106 | bic r2, r2, r0 ; clear mask in the cpsr | |
| 107 | and r1, r1, r0 ; clear bits outside the mask in the input | |
| 108 | orr r2, r2, r1 ; set field | |
| 109 | msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) | |
| 110 | mov sp, r3 ; restore stack pointer | |
| 111 | ldmfd sp!, {r4-r12, lr} ; restore registers | |
| 112 | bx lr ; return (hopefully thumb-safe!) | |
| 113 | ||
| 114 | CPSRRead | |
| 115 | mrs r0, cpsr | |
| 116 | bx lr | |
| 117 | ||
| 118 | END | |
| 119 | ||
| 120 |