[mirror_edk2.git] / ArmPkg / Library / ArmMmuLib / AArch64 / ArmMmuLibCore.c

/** @file\r
*  File managing the MMU for ARMv8 architecture\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*  Copyright (c) 2016, Linaro Limited. All rights reserved.\r
*  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Uefi.h>\r
#include <Chipset/AArch64.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/CacheMaintenanceLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/ArmLib.h>\r
#include <Library/ArmMmuLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
\r
// We use this index definition to define an invalid block entry\r
#define TT_ATTR_INDX_INVALID    ((UINT32)~0)\r
\r
STATIC\r
UINT64\r
ArmMemoryAttributeToPageAttribute (\r
  IN ARM_MEMORY_REGION_ATTRIBUTES  Attributes\r
  )\r
{\r
  switch (Attributes) {\r
  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r
  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r
    return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
\r
  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
    return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
\r
  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
    return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
\r
  // Uncached and device mappings are treated as outer shareable by default,\r
  case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
    return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
\r
  default:\r
    ASSERT(0);\r
  case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
    if (ArmReadCurrentEL () == AARCH64_EL2)\r
      return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r
    else\r
      return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r
  }\r
}\r
\r
UINT64\r
PageAttributeToGcdAttribute (\r
  IN UINT64 PageAttributes\r
  )\r
{\r
  UINT64  GcdAttributes;\r
\r
  switch (PageAttributes & TT_ATTR_INDX_MASK) {\r
  case TT_ATTR_INDX_DEVICE_MEMORY:\r
    GcdAttributes = EFI_MEMORY_UC;\r
    break;\r
  case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:\r
    GcdAttributes = EFI_MEMORY_WC;\r
    break;\r
  case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:\r
    GcdAttributes = EFI_MEMORY_WT;\r
    break;\r
  case TT_ATTR_INDX_MEMORY_WRITE_BACK:\r
    GcdAttributes = EFI_MEMORY_WB;\r
    break;\r
  default:\r
    DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));\r
    ASSERT (0);\r
    // The Global Coherency Domain (GCD) value is defined as a bit set.\r
    // Returning 0 means no attribute has been set.\r
    GcdAttributes = 0;\r
  }\r
\r
  // Determine protection attributes\r
  if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {\r
    // Read only cases map to write-protect\r
    GcdAttributes |= EFI_MEMORY_RO;\r
  }\r
\r
  // Process eXecute Never attribute\r
  if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {\r
    GcdAttributes |= EFI_MEMORY_XP;\r
  }\r
\r
  return GcdAttributes;\r
}\r
\r
#define MIN_T0SZ        16\r
#define BITS_PER_LEVEL  9\r
\r
VOID\r
GetRootTranslationTableInfo (\r
  IN UINTN     T0SZ,\r
  OUT UINTN   *TableLevel,\r
  OUT UINTN   *TableEntryCount\r
  )\r
{\r
  // Get the level of the root table\r
  if (TableLevel) {\r
    *TableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;\r
  }\r
\r
  if (TableEntryCount) {\r
    *TableEntryCount = 1UL << (BITS_PER_LEVEL - (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL);\r
  }\r
}\r
\r
STATIC\r
VOID\r
ReplaceLiveEntry (\r
  IN  UINT64  *Entry,\r
  IN  UINT64  Value\r
  )\r
{\r
  if (!ArmMmuEnabled ()) {\r
    *Entry = Value;\r
  } else {\r
    ArmReplaceLiveTranslationEntry (Entry, Value);\r
  }\r
}\r
\r
STATIC\r
VOID\r
LookupAddresstoRootTable (\r
  IN  UINT64  MaxAddress,\r
  OUT UINTN  *T0SZ,\r
  OUT UINTN  *TableEntryCount\r
  )\r
{\r
  UINTN TopBit;\r
\r
  // Check the parameters are not NULL\r
  ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));\r
\r
  // Look for the highest bit set in MaxAddress\r
  for (TopBit = 63; TopBit != 0; TopBit--) {\r
    if ((1ULL << TopBit) & MaxAddress) {\r
      // MaxAddress top bit is found\r
      TopBit = TopBit + 1;\r
      break;\r
    }\r
  }\r
  ASSERT (TopBit != 0);\r
\r
  // Calculate T0SZ from the top bit of the MaxAddress\r
  *T0SZ = 64 - TopBit;\r
\r
  // Get the Table info from T0SZ\r
  GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);\r
}\r
\r
STATIC\r
UINT64*\r
GetBlockEntryListFromAddress (\r
  IN  UINT64       *RootTable,\r
  IN  UINT64        RegionStart,\r
  OUT UINTN        *TableLevel,\r
  IN OUT UINT64    *BlockEntrySize,\r
  OUT UINT64      **LastBlockEntry\r
  )\r
{\r
  UINTN   RootTableLevel;\r
  UINTN   RootTableEntryCount;\r
  UINT64 *TranslationTable;\r
  UINT64 *BlockEntry;\r
  UINT64 *SubTableBlockEntry;\r
  UINT64  BlockEntryAddress;\r
  UINTN   BaseAddressAlignment;\r
  UINTN   PageLevel;\r
  UINTN   Index;\r
  UINTN   IndexLevel;\r
  UINTN   T0SZ;\r
  UINT64  Attributes;\r
  UINT64  TableAttributes;\r
\r
  // Initialize variable\r
  BlockEntry = NULL;\r
\r
  // Ensure the parameters are valid\r
  if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {\r
    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r
    return NULL;\r
  }\r
\r
  // Ensure the Region is aligned on 4KB boundary\r
  if ((RegionStart & (SIZE_4KB - 1)) != 0) {\r
    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r
    return NULL;\r
  }\r
\r
  // Ensure the required size is aligned on 4KB boundary and not 0\r
  if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {\r
    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r
    return NULL;\r
  }\r
\r
  T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;\r
  // Get the Table info from T0SZ\r
  GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);\r
\r
  // If the start address is 0x0 then we use the size of the region to identify the alignment\r
  if (RegionStart == 0) {\r
    // Identify the highest possible alignment for the Region Size\r
    BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);\r
  } else {\r
    // Identify the highest possible alignment for the Base Address\r
    BaseAddressAlignment = LowBitSet64 (RegionStart);\r
  }\r
\r
  // Identify the Page Level the RegionStart must belong to. Note that PageLevel\r
  // should be at least 1 since block translations are not supported at level 0\r
  PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);\r
\r
  // If the required size is smaller than the current block size then we need to go to the page below.\r
  // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment\r
  // of the allocation size\r
  while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {\r
    // It does not fit so we need to go a page level above\r
    PageLevel++;\r
  }\r
\r
  //\r
  // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries\r
  //\r
\r
  TranslationTable = RootTable;\r
  for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {\r
    BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);\r
\r
    if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {\r
      // Go to the next table\r
      TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);\r
\r
      // If we are at the last level then update the last level to next level\r
      if (IndexLevel == PageLevel) {\r
        // Enter the next level\r
        PageLevel++;\r
      }\r
    } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {\r
      // If we are not at the last level then we need to split this BlockEntry\r
      if (IndexLevel != PageLevel) {\r
        // Retrieve the attributes from the block entry\r
        Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;\r
\r
        // Convert the block entry attributes into Table descriptor attributes\r
        TableAttributes = TT_TABLE_AP_NO_PERMISSION;\r
        if (Attributes & TT_NS) {\r
          TableAttributes = TT_TABLE_NS;\r
        }\r
\r
        // Get the address corresponding at this entry\r
        BlockEntryAddress = RegionStart;\r
        BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);\r
        // Shift back to right to set zero before the effective address\r
        BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);\r
\r
        // Set the correct entry type for the next page level\r
        if ((IndexLevel + 1) == 3) {\r
          Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;\r
        } else {\r
          Attributes |= TT_TYPE_BLOCK_ENTRY;\r
        }\r
\r
        // Create a new translation table\r
        TranslationTable = AllocatePages (1);\r
        if (TranslationTable == NULL) {\r
          return NULL;\r
        }\r
\r
        // Populate the newly created lower level table\r
        SubTableBlockEntry = TranslationTable;\r
        for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {\r
          *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));\r
          SubTableBlockEntry++;\r
        }\r
\r
        // Fill the BlockEntry with the new TranslationTable\r
        ReplaceLiveEntry (BlockEntry,\r
          ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY);\r
      }\r
    } else {\r
      if (IndexLevel != PageLevel) {\r
        //\r
        // Case when we have an Invalid Entry and we are at a page level above of the one targetted.\r
        //\r
\r
        // Create a new translation table\r
        TranslationTable = AllocatePages (1);\r
        if (TranslationTable == NULL) {\r
          return NULL;\r
        }\r
\r
        ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));\r
\r
        // Fill the new BlockEntry with the TranslationTable\r
        *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;\r
      }\r
    }\r
  }\r
\r
  // Expose the found PageLevel to the caller\r
  *TableLevel = PageLevel;\r
\r
  // Now, we have the Table Level we can get the Block Size associated to this table\r
  *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);\r
\r
  // The last block of the root table depends on the number of entry in this table,\r
  // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.\r
  *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable,\r
      (PageLevel == RootTableLevel) ? RootTableEntryCount : TT_ENTRY_COUNT);\r
\r
  return BlockEntry;\r
}\r
\r
STATIC\r
EFI_STATUS\r
UpdateRegionMapping (\r
  IN  UINT64  *RootTable,\r
  IN  UINT64  RegionStart,\r
  IN  UINT64  RegionLength,\r
  IN  UINT64  Attributes,\r
  IN  UINT64  BlockEntryMask\r
  )\r
{\r
  UINT32  Type;\r
  UINT64  *BlockEntry;\r
  UINT64  *LastBlockEntry;\r
  UINT64  BlockEntrySize;\r
  UINTN   TableLevel;\r
\r
  // Ensure the Length is aligned on 4KB boundary\r
  if ((RegionLength == 0) || ((RegionLength & (SIZE_4KB - 1)) != 0)) {\r
    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  do {\r
    // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor\r
    // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor\r
    BlockEntrySize = RegionLength;\r
    BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);\r
    if (BlockEntry == NULL) {\r
      // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables\r
      return EFI_OUT_OF_RESOURCES;\r
    }\r
\r
    if (TableLevel != 3) {\r
      Type = TT_TYPE_BLOCK_ENTRY;\r
    } else {\r
      Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;\r
    }\r
\r
    do {\r
      // Fill the Block Entry with attribute and output block address\r
      *BlockEntry &= BlockEntryMask;\r
      *BlockEntry |= (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;\r
\r
      // Go to the next BlockEntry\r
      RegionStart += BlockEntrySize;\r
      RegionLength -= BlockEntrySize;\r
      BlockEntry++;\r
\r
      // Break the inner loop when next block is a table\r
      // Rerun GetBlockEntryListFromAddress to avoid page table memory leak\r
      if (TableLevel != 3 && BlockEntry <= LastBlockEntry &&\r
          (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r
            break;\r
      }\r
    } while ((RegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));\r
  } while (RegionLength != 0);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
STATIC\r
EFI_STATUS\r
FillTranslationTable (\r
  IN  UINT64                        *RootTable,\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion\r
  )\r
{\r
  return UpdateRegionMapping (\r
           RootTable,\r
           MemoryRegion->VirtualBase,\r
           MemoryRegion->Length,\r
           ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,\r
           0\r
           );\r
}\r
\r
STATIC\r
UINT64\r
GcdAttributeToPageAttribute (\r
  IN UINT64 GcdAttributes\r
  )\r
{\r
  UINT64 PageAttributes;\r
\r
  switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {\r
  case EFI_MEMORY_UC:\r
    PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r
    break;\r
  case EFI_MEMORY_WC:\r
    PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
    break;\r
  case EFI_MEMORY_WT:\r
    PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
    break;\r
  case EFI_MEMORY_WB:\r
    PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
    break;\r
  default:\r
    PageAttributes = TT_ATTR_INDX_MASK;\r
    break;\r
  }\r
\r
  if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||\r
      (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {\r
    if (ArmReadCurrentEL () == AARCH64_EL2) {\r
      PageAttributes |= TT_XN_MASK;\r
    } else {\r
      PageAttributes |= TT_UXN_MASK | TT_PXN_MASK;\r
    }\r
  }\r
\r
  if ((GcdAttributes & EFI_MEMORY_RO) != 0) {\r
    PageAttributes |= TT_AP_RO_RO;\r
  }\r
\r
  return PageAttributes | TT_AF;\r
}\r
\r
EFI_STATUS\r
ArmSetMemoryAttributes (\r
  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN UINT64                    Length,\r
  IN UINT64                    Attributes\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  UINT64                      *TranslationTable;\r
  UINT64                       PageAttributes;\r
  UINT64                       PageAttributeMask;\r
\r
  PageAttributes = GcdAttributeToPageAttribute (Attributes);\r
  PageAttributeMask = 0;\r
\r
  if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {\r
    //\r
    // No memory type was set in Attributes, so we are going to update the\r
    // permissions only.\r
    //\r
    PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;\r
    PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |\r
                          TT_PXN_MASK | TT_XN_MASK);\r
  }\r
\r
  TranslationTable = ArmGetTTBR0BaseAddress ();\r
\r
  Status = UpdateRegionMapping (\r
             TranslationTable,\r
             BaseAddress,\r
             Length,\r
             PageAttributes,\r
             PageAttributeMask);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  // Invalidate all TLB entries so changes are synced\r
  ArmInvalidateTlb ();\r
\r
  return EFI_SUCCESS;\r
}\r
\r
STATIC\r
EFI_STATUS\r
SetMemoryRegionAttribute (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length,\r
  IN  UINT64                    Attributes,\r
  IN  UINT64                    BlockEntryMask\r
  )\r
{\r
  EFI_STATUS                   Status;\r
  UINT64                       *RootTable;\r
\r
  RootTable = ArmGetTTBR0BaseAddress ();\r
\r
  Status = UpdateRegionMapping (RootTable, BaseAddress, Length, Attributes, BlockEntryMask);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  // Invalidate all TLB entries so changes are synced\r
  ArmInvalidateTlb ();\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
ArmSetMemoryRegionNoExec (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  )\r
{\r
  UINT64    Val;\r
\r
  if (ArmReadCurrentEL () == AARCH64_EL1) {\r
    Val = TT_PXN_MASK | TT_UXN_MASK;\r
  } else {\r
    Val = TT_XN_MASK;\r
  }\r
\r
  return SetMemoryRegionAttribute (\r
           BaseAddress,\r
           Length,\r
           Val,\r
           ~TT_ADDRESS_MASK_BLOCK_ENTRY);\r
}\r
\r
EFI_STATUS\r
ArmClearMemoryRegionNoExec (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  )\r
{\r
  UINT64 Mask;\r
\r
  // XN maps to UXN in the EL1&0 translation regime\r
  Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);\r
\r
  return SetMemoryRegionAttribute (\r
           BaseAddress,\r
           Length,\r
           0,\r
           Mask);\r
}\r
\r
EFI_STATUS\r
ArmSetMemoryRegionReadOnly (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  )\r
{\r
  return SetMemoryRegionAttribute (\r
           BaseAddress,\r
           Length,\r
           TT_AP_RO_RO,\r
           ~TT_ADDRESS_MASK_BLOCK_ENTRY);\r
}\r
\r
EFI_STATUS\r
ArmClearMemoryRegionReadOnly (\r
  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
  IN  UINT64                    Length\r
  )\r
{\r
  return SetMemoryRegionAttribute (\r
           BaseAddress,\r
           Length,\r
           TT_AP_RW_RW,\r
           ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,\r
  OUT VOID                         **TranslationTableBase OPTIONAL,\r
  OUT UINTN                         *TranslationTableSize OPTIONAL\r
  )\r
{\r
  VOID*                         TranslationTable;\r
  UINT32                        TranslationTableAttribute;\r
  UINT64                        MaxAddress;\r
  UINTN                         T0SZ;\r
  UINTN                         RootTableEntryCount;\r
  UINT64                        TCR;\r
  EFI_STATUS                    Status;\r
\r
  if(MemoryTable == NULL) {\r
    ASSERT (MemoryTable != NULL);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Limit the virtual address space to what we can actually use: UEFI\r
  // mandates a 1:1 mapping, so no point in making the virtual address\r
  // space larger than the physical address space. We also have to take\r
  // into account the architectural limitations that result from UEFI's\r
  // use of 4 KB pages.\r
  //\r
  MaxAddress = MIN (LShiftU64 (1ULL, ArmGetPhysicalAddressBits ()) - 1,\r
                    MAX_ALLOC_ADDRESS);\r
\r
  // Lookup the Table Level to get the information\r
  LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);\r
\r
  //\r
  // Set TCR that allows us to retrieve T0SZ in the subsequent functions\r
  //\r
  // Ideally we will be running at EL2, but should support EL1 as well.\r
  // UEFI should not run at EL3.\r
  if (ArmReadCurrentEL () == AARCH64_EL2) {\r
    //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2\r
    TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;\r
\r
    // Set the Physical Address Size using MaxAddress\r
    if (MaxAddress < SIZE_4GB) {\r
      TCR |= TCR_PS_4GB;\r
    } else if (MaxAddress < SIZE_64GB) {\r
      TCR |= TCR_PS_64GB;\r
    } else if (MaxAddress < SIZE_1TB) {\r
      TCR |= TCR_PS_1TB;\r
    } else if (MaxAddress < SIZE_4TB) {\r
      TCR |= TCR_PS_4TB;\r
    } else if (MaxAddress < SIZE_16TB) {\r
      TCR |= TCR_PS_16TB;\r
    } else if (MaxAddress < SIZE_256TB) {\r
      TCR |= TCR_PS_256TB;\r
    } else {\r
      DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r
      ASSERT (0); // Bigger than 48-bit memory space are not supported\r
      return EFI_UNSUPPORTED;\r
    }\r
  } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r
    // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.\r
    TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;\r
\r
    // Set the Physical Address Size using MaxAddress\r
    if (MaxAddress < SIZE_4GB) {\r
      TCR |= TCR_IPS_4GB;\r
    } else if (MaxAddress < SIZE_64GB) {\r
      TCR |= TCR_IPS_64GB;\r
    } else if (MaxAddress < SIZE_1TB) {\r
      TCR |= TCR_IPS_1TB;\r
    } else if (MaxAddress < SIZE_4TB) {\r
      TCR |= TCR_IPS_4TB;\r
    } else if (MaxAddress < SIZE_16TB) {\r
      TCR |= TCR_IPS_16TB;\r
    } else if (MaxAddress < SIZE_256TB) {\r
      TCR |= TCR_IPS_256TB;\r
    } else {\r
      DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));\r
      ASSERT (0); // Bigger than 48-bit memory space are not supported\r
      return EFI_UNSUPPORTED;\r
    }\r
  } else {\r
    ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Translation table walks are always cache coherent on ARMv8-A, so cache\r
  // maintenance on page tables is never needed. Since there is a risk of\r
  // loss of coherency when using mismatched attributes, and given that memory\r
  // is mapped cacheable except for extraordinary cases (such as non-coherent\r
  // DMA), have the page table walker perform cached accesses as well, and\r
  // assert below that that matches the attributes we use for CPU accesses to\r
  // the region.\r
  //\r
  TCR |= TCR_SH_INNER_SHAREABLE |\r
         TCR_RGN_OUTER_WRITE_BACK_ALLOC |\r
         TCR_RGN_INNER_WRITE_BACK_ALLOC;\r
\r
  // Set TCR\r
  ArmSetTCR (TCR);\r
\r
  // Allocate pages for translation table\r
  TranslationTable = AllocatePages (1);\r
  if (TranslationTable == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
  // We set TTBR0 just after allocating the table to retrieve its location from the subsequent\r
  // functions without needing to pass this value across the functions. The MMU is only enabled\r
  // after the translation tables are populated.\r
  ArmSetTTBR0 (TranslationTable);\r
\r
  if (TranslationTableBase != NULL) {\r
    *TranslationTableBase = TranslationTable;\r
  }\r
\r
  if (TranslationTableSize != NULL) {\r
    *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);\r
  }\r
\r
  ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));\r
\r
  // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs\r
  ArmDisableMmu ();\r
  ArmDisableDataCache ();\r
  ArmDisableInstructionCache ();\r
\r
  // Make sure nothing sneaked into the cache\r
  ArmCleanInvalidateDataCache ();\r
  ArmInvalidateInstructionCache ();\r
\r
  TranslationTableAttribute = TT_ATTR_INDX_INVALID;\r
  while (MemoryTable->Length != 0) {\r
\r
    DEBUG_CODE_BEGIN ();\r
      // Find the memory attribute for the Translation Table\r
      if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&\r
          (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +\r
                                                          MemoryTable->Length) {\r
        TranslationTableAttribute = MemoryTable->Attributes;\r
      }\r
    DEBUG_CODE_END ();\r
\r
    Status = FillTranslationTable (TranslationTable, MemoryTable);\r
    if (EFI_ERROR (Status)) {\r
      goto FREE_TRANSLATION_TABLE;\r
    }\r
    MemoryTable++;\r
  }\r
\r
  ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ||\r
          TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK);\r
\r
  ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |                      // mapped to EFI_MEMORY_UC\r
              MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC\r
              MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT\r
              MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK));       // mapped to EFI_MEMORY_WB\r
\r
  ArmDisableAlignmentCheck ();\r
  ArmEnableStackAlignmentCheck ();\r
  ArmEnableInstructionCache ();\r
  ArmEnableDataCache ();\r
\r
  ArmEnableMmu ();\r
  return EFI_SUCCESS;\r
\r
FREE_TRANSLATION_TABLE:\r
  FreePages (TranslationTable, 1);\r
  return Status;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
ArmMmuBaseLibConstructor (\r
  VOID\r
  )\r
{\r
  extern UINT32 ArmReplaceLiveTranslationEntrySize;\r
\r
  //\r
  // The ArmReplaceLiveTranslationEntry () helper function may be invoked\r
  // with the MMU off so we have to ensure that it gets cleaned to the PoC\r
  //\r
  WriteBackDataCacheRange (ArmReplaceLiveTranslationEntry,\r
    ArmReplaceLiveTranslationEntrySize);\r
\r
  return RETURN_SUCCESS;\r
}\r