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d7f03464 AB |
1 | /** @file\r |
2 | * File managing the MMU for ARMv8 architecture\r | |
3 | *\r | |
191fa79b | 4 | * Copyright (c) 2011-2020, ARM Limited. All rights reserved.\r |
d7f03464 | 5 | * Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
b7a09b71 | 6 | * Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r |
d7f03464 | 7 | *\r |
4059386c | 8 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
d7f03464 AB |
9 | *\r |
10 | **/\r | |
11 | \r | |
12 | #include <Uefi.h>\r | |
13 | #include <Chipset/AArch64.h>\r | |
14 | #include <Library/BaseMemoryLib.h>\r | |
15 | #include <Library/CacheMaintenanceLib.h>\r | |
16 | #include <Library/MemoryAllocationLib.h>\r | |
17 | #include <Library/ArmLib.h>\r | |
18 | #include <Library/ArmMmuLib.h>\r | |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | \r | |
22 | // We use this index definition to define an invalid block entry\r | |
23 | #define TT_ATTR_INDX_INVALID ((UINT32)~0)\r | |
24 | \r | |
25 | STATIC\r | |
26 | UINT64\r | |
27 | ArmMemoryAttributeToPageAttribute (\r | |
28 | IN ARM_MEMORY_REGION_ATTRIBUTES Attributes\r | |
29 | )\r | |
30 | {\r | |
31 | switch (Attributes) {\r | |
829633e3 PL |
32 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:\r |
33 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:\r | |
34 | return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r | |
35 | \r | |
d7f03464 AB |
36 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r |
37 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r | |
38 | return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r | |
39 | \r | |
40 | case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r | |
41 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r | |
42 | return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r | |
43 | \r | |
44 | // Uncached and device mappings are treated as outer shareable by default,\r | |
45 | case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r | |
46 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r | |
47 | return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r | |
48 | \r | |
49 | default:\r | |
4249278a | 50 | ASSERT (0);\r |
d7f03464 AB |
51 | case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r |
52 | case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r | |
53 | if (ArmReadCurrentEL () == AARCH64_EL2)\r | |
54 | return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;\r | |
55 | else\r | |
56 | return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;\r | |
57 | }\r | |
58 | }\r | |
59 | \r | |
e93cb72e AB |
60 | #define MIN_T0SZ 16\r |
61 | #define BITS_PER_LEVEL 9\r | |
db0f8c2f AB |
62 | #define MAX_VA_BITS 48\r |
63 | \r | |
64 | STATIC\r | |
65 | UINTN\r | |
66 | GetRootTableEntryCount (\r | |
67 | IN UINTN T0SZ\r | |
68 | )\r | |
69 | {\r | |
70 | return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;\r | |
71 | }\r | |
d7f03464 | 72 | \r |
991c5d89 AB |
73 | STATIC\r |
74 | UINTN\r | |
75 | GetRootTableLevel (\r | |
76 | IN UINTN T0SZ\r | |
d7f03464 AB |
77 | )\r |
78 | {\r | |
991c5d89 | 79 | return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;\r |
d7f03464 AB |
80 | }\r |
81 | \r | |
82 | STATIC\r | |
83 | VOID\r | |
191fa79b | 84 | ReplaceTableEntry (\r |
d7f03464 | 85 | IN UINT64 *Entry,\r |
d5788777 | 86 | IN UINT64 Value,\r |
191fa79b AB |
87 | IN UINT64 RegionStart,\r |
88 | IN BOOLEAN IsLiveBlockMapping\r | |
d7f03464 AB |
89 | )\r |
90 | {\r | |
191fa79b | 91 | if (!ArmMmuEnabled () || !IsLiveBlockMapping) {\r |
d7f03464 | 92 | *Entry = Value;\r |
191fa79b | 93 | ArmUpdateTranslationTableEntry (Entry, (VOID *)(UINTN)RegionStart);\r |
d7f03464 | 94 | } else {\r |
d5788777 | 95 | ArmReplaceLiveTranslationEntry (Entry, Value, RegionStart);\r |
d7f03464 AB |
96 | }\r |
97 | }\r | |
98 | \r | |
99 | STATIC\r | |
100 | VOID\r | |
191fa79b | 101 | FreePageTablesRecursive (\r |
d390920e AB |
102 | IN UINT64 *TranslationTable,\r |
103 | IN UINTN Level\r | |
d7f03464 AB |
104 | )\r |
105 | {\r | |
191fa79b | 106 | UINTN Index;\r |
d7f03464 | 107 | \r |
d390920e AB |
108 | ASSERT (Level <= 3);\r |
109 | \r | |
110 | if (Level < 3) {\r | |
111 | for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {\r | |
112 | if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {\r | |
113 | FreePageTablesRecursive ((VOID *)(UINTN)(TranslationTable[Index] &\r | |
114 | TT_ADDRESS_MASK_BLOCK_ENTRY),\r | |
115 | Level + 1);\r | |
116 | }\r | |
d7f03464 AB |
117 | }\r |
118 | }\r | |
191fa79b | 119 | FreePages (TranslationTable, 1);\r |
d7f03464 AB |
120 | }\r |
121 | \r | |
5fc89953 AB |
122 | STATIC\r |
123 | BOOLEAN\r | |
124 | IsBlockEntry (\r | |
125 | IN UINT64 Entry,\r | |
126 | IN UINTN Level\r | |
127 | )\r | |
128 | {\r | |
129 | if (Level == 3) {\r | |
130 | return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3;\r | |
131 | }\r | |
132 | return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY;\r | |
133 | }\r | |
134 | \r | |
135 | STATIC\r | |
136 | BOOLEAN\r | |
137 | IsTableEntry (\r | |
138 | IN UINT64 Entry,\r | |
139 | IN UINTN Level\r | |
140 | )\r | |
141 | {\r | |
142 | if (Level == 3) {\r | |
143 | //\r | |
144 | // TT_TYPE_TABLE_ENTRY aliases TT_TYPE_BLOCK_ENTRY_LEVEL3\r | |
145 | // so we need to take the level into account as well.\r | |
146 | //\r | |
147 | return FALSE;\r | |
148 | }\r | |
149 | return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY;\r | |
150 | }\r | |
151 | \r | |
d7f03464 | 152 | STATIC\r |
191fa79b AB |
153 | EFI_STATUS\r |
154 | UpdateRegionMappingRecursive (\r | |
155 | IN UINT64 RegionStart,\r | |
156 | IN UINT64 RegionEnd,\r | |
157 | IN UINT64 AttributeSetMask,\r | |
158 | IN UINT64 AttributeClearMask,\r | |
159 | IN UINT64 *PageTable,\r | |
160 | IN UINTN Level\r | |
d7f03464 AB |
161 | )\r |
162 | {\r | |
191fa79b AB |
163 | UINTN BlockShift;\r |
164 | UINT64 BlockMask;\r | |
165 | UINT64 BlockEnd;\r | |
166 | UINT64 *Entry;\r | |
167 | UINT64 EntryValue;\r | |
168 | VOID *TranslationTable;\r | |
169 | EFI_STATUS Status;\r | |
d7f03464 | 170 | \r |
191fa79b | 171 | ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);\r |
d7f03464 | 172 | \r |
191fa79b AB |
173 | BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ;\r |
174 | BlockMask = MAX_UINT64 >> BlockShift;\r | |
d7f03464 | 175 | \r |
191fa79b AB |
176 | DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTION__,\r |
177 | Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask));\r | |
d7f03464 | 178 | \r |
191fa79b AB |
179 | for (; RegionStart < RegionEnd; RegionStart = BlockEnd) {\r |
180 | BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);\r | |
181 | Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];\r | |
d7f03464 | 182 | \r |
191fa79b AB |
183 | //\r |
184 | // If RegionStart or BlockEnd is not aligned to the block size at this\r | |
185 | // level, we will have to create a table mapping in order to map less\r | |
186 | // than a block, and recurse to create the block or page entries at\r | |
187 | // the next level. No block mappings are allowed at all at level 0,\r | |
188 | // so in that case, we have to recurse unconditionally.\r | |
f7079d1b AB |
189 | // If we are changing a table entry and the AttributeClearMask is non-zero,\r |
190 | // we cannot replace it with a block entry without potentially losing\r | |
191 | // attribute information, so keep the table entry in that case.\r | |
191fa79b | 192 | //\r |
f7079d1b AB |
193 | if (Level == 0 || ((RegionStart | BlockEnd) & BlockMask) != 0 ||\r |
194 | (IsTableEntry (*Entry, Level) && AttributeClearMask != 0)) {\r | |
191fa79b | 195 | ASSERT (Level < 3);\r |
d7f03464 | 196 | \r |
5fc89953 | 197 | if (!IsTableEntry (*Entry, Level)) {\r |
191fa79b AB |
198 | //\r |
199 | // No table entry exists yet, so we need to allocate a page table\r | |
200 | // for the next level.\r | |
201 | //\r | |
674e127e | 202 | TranslationTable = AllocatePages (1);\r |
d7f03464 | 203 | if (TranslationTable == NULL) {\r |
191fa79b | 204 | return EFI_OUT_OF_RESOURCES;\r |
d7f03464 AB |
205 | }\r |
206 | \r | |
748fea62 AB |
207 | if (!ArmMmuEnabled ()) {\r |
208 | //\r | |
209 | // Make sure we are not inadvertently hitting in the caches\r | |
210 | // when populating the page tables.\r | |
211 | //\r | |
212 | InvalidateDataCacheRange (TranslationTable, EFI_PAGE_SIZE);\r | |
213 | }\r | |
214 | \r | |
f7079d1b AB |
215 | ZeroMem (TranslationTable, EFI_PAGE_SIZE);\r |
216 | \r | |
5fc89953 | 217 | if (IsBlockEntry (*Entry, Level)) {\r |
191fa79b AB |
218 | //\r |
219 | // We are splitting an existing block entry, so we have to populate\r | |
220 | // the new table with the attributes of the block entry it replaces.\r | |
221 | //\r | |
222 | Status = UpdateRegionMappingRecursive (RegionStart & ~BlockMask,\r | |
223 | (RegionStart | BlockMask) + 1, *Entry & TT_ATTRIBUTES_MASK,\r | |
224 | 0, TranslationTable, Level + 1);\r | |
225 | if (EFI_ERROR (Status)) {\r | |
226 | //\r | |
227 | // The range we passed to UpdateRegionMappingRecursive () is block\r | |
228 | // aligned, so it is guaranteed that no further pages were allocated\r | |
229 | // by it, and so we only have to free the page we allocated here.\r | |
230 | //\r | |
231 | FreePages (TranslationTable, 1);\r | |
232 | return Status;\r | |
233 | }\r | |
d7f03464 | 234 | }\r |
191fa79b AB |
235 | } else {\r |
236 | TranslationTable = (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOCK_ENTRY);\r | |
d7f03464 | 237 | }\r |
d7f03464 | 238 | \r |
191fa79b AB |
239 | //\r |
240 | // Recurse to the next level\r | |
241 | //\r | |
242 | Status = UpdateRegionMappingRecursive (RegionStart, BlockEnd,\r | |
243 | AttributeSetMask, AttributeClearMask, TranslationTable,\r | |
244 | Level + 1);\r | |
245 | if (EFI_ERROR (Status)) {\r | |
5fc89953 | 246 | if (!IsTableEntry (*Entry, Level)) {\r |
191fa79b AB |
247 | //\r |
248 | // We are creating a new table entry, so on failure, we can free all\r | |
249 | // allocations we made recursively, given that the whole subhierarchy\r | |
250 | // has not been wired into the live page tables yet. (This is not\r | |
251 | // possible for existing table entries, since we cannot revert the\r | |
252 | // modifications we made to the subhierarchy it represents.)\r | |
253 | //\r | |
d390920e | 254 | FreePageTablesRecursive (TranslationTable, Level + 1);\r |
d7f03464 | 255 | }\r |
191fa79b AB |
256 | return Status;\r |
257 | }\r | |
d7f03464 | 258 | \r |
5fc89953 | 259 | if (!IsTableEntry (*Entry, Level)) {\r |
191fa79b AB |
260 | EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;\r |
261 | ReplaceTableEntry (Entry, EntryValue, RegionStart,\r | |
5fc89953 | 262 | IsBlockEntry (*Entry, Level));\r |
d7f03464 | 263 | }\r |
191fa79b AB |
264 | } else {\r |
265 | EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;\r | |
266 | EntryValue |= RegionStart;\r | |
267 | EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3\r | |
268 | : TT_TYPE_BLOCK_ENTRY;\r | |
269 | \r | |
f7079d1b AB |
270 | if (IsTableEntry (*Entry, Level)) {\r |
271 | //\r | |
272 | // We are replacing a table entry with a block entry. This is only\r | |
273 | // possible if we are keeping none of the original attributes.\r | |
274 | // We can free the table entry's page table, and all the ones below\r | |
275 | // it, since we are dropping the only possible reference to it.\r | |
276 | //\r | |
277 | ASSERT (AttributeClearMask == 0);\r | |
278 | TranslationTable = (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOCK_ENTRY);\r | |
279 | ReplaceTableEntry (Entry, EntryValue, RegionStart, TRUE);\r | |
280 | FreePageTablesRecursive (TranslationTable, Level + 1);\r | |
281 | } else {\r | |
282 | ReplaceTableEntry (Entry, EntryValue, RegionStart, FALSE);\r | |
283 | }\r | |
d7f03464 AB |
284 | }\r |
285 | }\r | |
191fa79b AB |
286 | return EFI_SUCCESS;\r |
287 | }\r | |
d7f03464 | 288 | \r |
d7f03464 | 289 | STATIC\r |
f49ea03d | 290 | EFI_STATUS\r |
d7f03464 | 291 | UpdateRegionMapping (\r |
d7f03464 AB |
292 | IN UINT64 RegionStart,\r |
293 | IN UINT64 RegionLength,\r | |
191fa79b AB |
294 | IN UINT64 AttributeSetMask,\r |
295 | IN UINT64 AttributeClearMask\r | |
d7f03464 AB |
296 | )\r |
297 | {\r | |
191fa79b AB |
298 | UINTN T0SZ;\r |
299 | \r | |
300 | if (((RegionStart | RegionLength) & EFI_PAGE_MASK)) {\r | |
f49ea03d | 301 | return EFI_INVALID_PARAMETER;\r |
d7f03464 AB |
302 | }\r |
303 | \r | |
191fa79b | 304 | T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;\r |
d7f03464 | 305 | \r |
191fa79b AB |
306 | return UpdateRegionMappingRecursive (RegionStart, RegionStart + RegionLength,\r |
307 | AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (),\r | |
991c5d89 | 308 | GetRootTableLevel (T0SZ));\r |
d7f03464 AB |
309 | }\r |
310 | \r | |
311 | STATIC\r | |
f49ea03d | 312 | EFI_STATUS\r |
d7f03464 AB |
313 | FillTranslationTable (\r |
314 | IN UINT64 *RootTable,\r | |
315 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r | |
316 | )\r | |
317 | {\r | |
318 | return UpdateRegionMapping (\r | |
d7f03464 AB |
319 | MemoryRegion->VirtualBase,\r |
320 | MemoryRegion->Length,\r | |
321 | ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,\r | |
322 | 0\r | |
323 | );\r | |
324 | }\r | |
325 | \r | |
e0307a7d AB |
326 | STATIC\r |
327 | UINT64\r | |
328 | GcdAttributeToPageAttribute (\r | |
329 | IN UINT64 GcdAttributes\r | |
330 | )\r | |
331 | {\r | |
332 | UINT64 PageAttributes;\r | |
333 | \r | |
334 | switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {\r | |
335 | case EFI_MEMORY_UC:\r | |
336 | PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r | |
337 | break;\r | |
338 | case EFI_MEMORY_WC:\r | |
339 | PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r | |
340 | break;\r | |
341 | case EFI_MEMORY_WT:\r | |
342 | PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r | |
343 | break;\r | |
344 | case EFI_MEMORY_WB:\r | |
345 | PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r | |
346 | break;\r | |
347 | default:\r | |
348 | PageAttributes = TT_ATTR_INDX_MASK;\r | |
349 | break;\r | |
350 | }\r | |
351 | \r | |
352 | if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||\r | |
353 | (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {\r | |
354 | if (ArmReadCurrentEL () == AARCH64_EL2) {\r | |
355 | PageAttributes |= TT_XN_MASK;\r | |
356 | } else {\r | |
357 | PageAttributes |= TT_UXN_MASK | TT_PXN_MASK;\r | |
358 | }\r | |
359 | }\r | |
360 | \r | |
361 | if ((GcdAttributes & EFI_MEMORY_RO) != 0) {\r | |
362 | PageAttributes |= TT_AP_RO_RO;\r | |
363 | }\r | |
364 | \r | |
365 | return PageAttributes | TT_AF;\r | |
366 | }\r | |
367 | \r | |
f49ea03d | 368 | EFI_STATUS\r |
521f3ced | 369 | ArmSetMemoryAttributes (\r |
d7f03464 AB |
370 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r |
371 | IN UINT64 Length,\r | |
d9c0d991 | 372 | IN UINT64 Attributes\r |
d7f03464 AB |
373 | )\r |
374 | {\r | |
e0307a7d AB |
375 | UINT64 PageAttributes;\r |
376 | UINT64 PageAttributeMask;\r | |
377 | \r | |
378 | PageAttributes = GcdAttributeToPageAttribute (Attributes);\r | |
379 | PageAttributeMask = 0;\r | |
380 | \r | |
381 | if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {\r | |
382 | //\r | |
383 | // No memory type was set in Attributes, so we are going to update the\r | |
384 | // permissions only.\r | |
385 | //\r | |
386 | PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;\r | |
387 | PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |\r | |
388 | TT_PXN_MASK | TT_XN_MASK);\r | |
389 | }\r | |
d7f03464 | 390 | \r |
191fa79b AB |
391 | return UpdateRegionMapping (BaseAddress, Length, PageAttributes,\r |
392 | PageAttributeMask);\r | |
d7f03464 AB |
393 | }\r |
394 | \r | |
395 | STATIC\r | |
f49ea03d | 396 | EFI_STATUS\r |
d7f03464 AB |
397 | SetMemoryRegionAttribute (\r |
398 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
399 | IN UINT64 Length,\r | |
400 | IN UINT64 Attributes,\r | |
401 | IN UINT64 BlockEntryMask\r | |
402 | )\r | |
403 | {\r | |
191fa79b | 404 | return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask);\r |
d7f03464 AB |
405 | }\r |
406 | \r | |
f49ea03d | 407 | EFI_STATUS\r |
d7f03464 AB |
408 | ArmSetMemoryRegionNoExec (\r |
409 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
410 | IN UINT64 Length\r | |
411 | )\r | |
412 | {\r | |
413 | UINT64 Val;\r | |
414 | \r | |
415 | if (ArmReadCurrentEL () == AARCH64_EL1) {\r | |
416 | Val = TT_PXN_MASK | TT_UXN_MASK;\r | |
417 | } else {\r | |
418 | Val = TT_XN_MASK;\r | |
419 | }\r | |
420 | \r | |
421 | return SetMemoryRegionAttribute (\r | |
422 | BaseAddress,\r | |
423 | Length,\r | |
424 | Val,\r | |
425 | ~TT_ADDRESS_MASK_BLOCK_ENTRY);\r | |
426 | }\r | |
427 | \r | |
f49ea03d | 428 | EFI_STATUS\r |
d7f03464 AB |
429 | ArmClearMemoryRegionNoExec (\r |
430 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
431 | IN UINT64 Length\r | |
432 | )\r | |
433 | {\r | |
434 | UINT64 Mask;\r | |
435 | \r | |
436 | // XN maps to UXN in the EL1&0 translation regime\r | |
437 | Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);\r | |
438 | \r | |
439 | return SetMemoryRegionAttribute (\r | |
440 | BaseAddress,\r | |
441 | Length,\r | |
442 | 0,\r | |
443 | Mask);\r | |
444 | }\r | |
445 | \r | |
f49ea03d | 446 | EFI_STATUS\r |
d7f03464 AB |
447 | ArmSetMemoryRegionReadOnly (\r |
448 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
449 | IN UINT64 Length\r | |
450 | )\r | |
451 | {\r | |
452 | return SetMemoryRegionAttribute (\r | |
453 | BaseAddress,\r | |
454 | Length,\r | |
455 | TT_AP_RO_RO,\r | |
456 | ~TT_ADDRESS_MASK_BLOCK_ENTRY);\r | |
457 | }\r | |
458 | \r | |
f49ea03d | 459 | EFI_STATUS\r |
d7f03464 AB |
460 | ArmClearMemoryRegionReadOnly (\r |
461 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
462 | IN UINT64 Length\r | |
463 | )\r | |
464 | {\r | |
465 | return SetMemoryRegionAttribute (\r | |
466 | BaseAddress,\r | |
467 | Length,\r | |
468 | TT_AP_RW_RW,\r | |
469 | ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));\r | |
470 | }\r | |
471 | \r | |
f49ea03d | 472 | EFI_STATUS\r |
d7f03464 AB |
473 | EFIAPI\r |
474 | ArmConfigureMmu (\r | |
475 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r | |
476 | OUT VOID **TranslationTableBase OPTIONAL,\r | |
477 | OUT UINTN *TranslationTableSize OPTIONAL\r | |
478 | )\r | |
479 | {\r | |
480 | VOID* TranslationTable;\r | |
db0f8c2f | 481 | UINTN MaxAddressBits;\r |
d7f03464 | 482 | UINT64 MaxAddress;\r |
d7f03464 AB |
483 | UINTN T0SZ;\r |
484 | UINTN RootTableEntryCount;\r | |
485 | UINT64 TCR;\r | |
f49ea03d | 486 | EFI_STATUS Status;\r |
d7f03464 | 487 | \r |
4249278a | 488 | if (MemoryTable == NULL) {\r |
d7f03464 | 489 | ASSERT (MemoryTable != NULL);\r |
f49ea03d | 490 | return EFI_INVALID_PARAMETER;\r |
d7f03464 AB |
491 | }\r |
492 | \r | |
e36b243c AB |
493 | //\r |
494 | // Limit the virtual address space to what we can actually use: UEFI\r | |
495 | // mandates a 1:1 mapping, so no point in making the virtual address\r | |
496 | // space larger than the physical address space. We also have to take\r | |
497 | // into account the architectural limitations that result from UEFI's\r | |
498 | // use of 4 KB pages.\r | |
499 | //\r | |
db0f8c2f AB |
500 | MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS);\r |
501 | MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;\r | |
d7f03464 | 502 | \r |
db0f8c2f AB |
503 | T0SZ = 64 - MaxAddressBits;\r |
504 | RootTableEntryCount = GetRootTableEntryCount (T0SZ);\r | |
d7f03464 AB |
505 | \r |
506 | //\r | |
507 | // Set TCR that allows us to retrieve T0SZ in the subsequent functions\r | |
508 | //\r | |
509 | // Ideally we will be running at EL2, but should support EL1 as well.\r | |
510 | // UEFI should not run at EL3.\r | |
511 | if (ArmReadCurrentEL () == AARCH64_EL2) {\r | |
512 | //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2\r | |
513 | TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;\r | |
514 | \r | |
515 | // Set the Physical Address Size using MaxAddress\r | |
516 | if (MaxAddress < SIZE_4GB) {\r | |
517 | TCR |= TCR_PS_4GB;\r | |
518 | } else if (MaxAddress < SIZE_64GB) {\r | |
519 | TCR |= TCR_PS_64GB;\r | |
520 | } else if (MaxAddress < SIZE_1TB) {\r | |
521 | TCR |= TCR_PS_1TB;\r | |
522 | } else if (MaxAddress < SIZE_4TB) {\r | |
523 | TCR |= TCR_PS_4TB;\r | |
524 | } else if (MaxAddress < SIZE_16TB) {\r | |
525 | TCR |= TCR_PS_16TB;\r | |
526 | } else if (MaxAddress < SIZE_256TB) {\r | |
527 | TCR |= TCR_PS_256TB;\r | |
528 | } else {\r | |
4249278a AB |
529 | DEBUG ((DEBUG_ERROR,\r |
530 | "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",\r | |
531 | MaxAddress));\r | |
d7f03464 | 532 | ASSERT (0); // Bigger than 48-bit memory space are not supported\r |
f49ea03d | 533 | return EFI_UNSUPPORTED;\r |
d7f03464 AB |
534 | }\r |
535 | } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r | |
536 | // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.\r | |
537 | TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;\r | |
538 | \r | |
539 | // Set the Physical Address Size using MaxAddress\r | |
540 | if (MaxAddress < SIZE_4GB) {\r | |
541 | TCR |= TCR_IPS_4GB;\r | |
542 | } else if (MaxAddress < SIZE_64GB) {\r | |
543 | TCR |= TCR_IPS_64GB;\r | |
544 | } else if (MaxAddress < SIZE_1TB) {\r | |
545 | TCR |= TCR_IPS_1TB;\r | |
546 | } else if (MaxAddress < SIZE_4TB) {\r | |
547 | TCR |= TCR_IPS_4TB;\r | |
548 | } else if (MaxAddress < SIZE_16TB) {\r | |
549 | TCR |= TCR_IPS_16TB;\r | |
550 | } else if (MaxAddress < SIZE_256TB) {\r | |
551 | TCR |= TCR_IPS_256TB;\r | |
552 | } else {\r | |
4249278a AB |
553 | DEBUG ((DEBUG_ERROR,\r |
554 | "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",\r | |
555 | MaxAddress));\r | |
d7f03464 | 556 | ASSERT (0); // Bigger than 48-bit memory space are not supported\r |
f49ea03d | 557 | return EFI_UNSUPPORTED;\r |
d7f03464 AB |
558 | }\r |
559 | } else {\r | |
560 | ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.\r | |
f49ea03d | 561 | return EFI_UNSUPPORTED;\r |
d7f03464 AB |
562 | }\r |
563 | \r | |
35718840 AB |
564 | //\r |
565 | // Translation table walks are always cache coherent on ARMv8-A, so cache\r | |
566 | // maintenance on page tables is never needed. Since there is a risk of\r | |
567 | // loss of coherency when using mismatched attributes, and given that memory\r | |
568 | // is mapped cacheable except for extraordinary cases (such as non-coherent\r | |
569 | // DMA), have the page table walker perform cached accesses as well, and\r | |
570 | // assert below that that matches the attributes we use for CPU accesses to\r | |
571 | // the region.\r | |
572 | //\r | |
573 | TCR |= TCR_SH_INNER_SHAREABLE |\r | |
574 | TCR_RGN_OUTER_WRITE_BACK_ALLOC |\r | |
575 | TCR_RGN_INNER_WRITE_BACK_ALLOC;\r | |
576 | \r | |
d7f03464 AB |
577 | // Set TCR\r |
578 | ArmSetTCR (TCR);\r | |
579 | \r | |
aa961dea AB |
580 | // Allocate pages for translation table\r |
581 | TranslationTable = AllocatePages (1);\r | |
d7f03464 | 582 | if (TranslationTable == NULL) {\r |
f49ea03d | 583 | return EFI_OUT_OF_RESOURCES;\r |
d7f03464 | 584 | }\r |
4249278a AB |
585 | //\r |
586 | // We set TTBR0 just after allocating the table to retrieve its location from\r | |
587 | // the subsequent functions without needing to pass this value across the\r | |
588 | // functions. The MMU is only enabled after the translation tables are\r | |
589 | // populated.\r | |
590 | //\r | |
d7f03464 AB |
591 | ArmSetTTBR0 (TranslationTable);\r |
592 | \r | |
593 | if (TranslationTableBase != NULL) {\r | |
594 | *TranslationTableBase = TranslationTable;\r | |
595 | }\r | |
596 | \r | |
597 | if (TranslationTableSize != NULL) {\r | |
4249278a | 598 | *TranslationTableSize = RootTableEntryCount * sizeof (UINT64);\r |
d7f03464 AB |
599 | }\r |
600 | \r | |
748fea62 AB |
601 | //\r |
602 | // Make sure we are not inadvertently hitting in the caches\r | |
603 | // when populating the page tables.\r | |
604 | //\r | |
605 | InvalidateDataCacheRange (TranslationTable,\r | |
4249278a AB |
606 | RootTableEntryCount * sizeof (UINT64));\r |
607 | ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));\r | |
d7f03464 | 608 | \r |
d7f03464 | 609 | while (MemoryTable->Length != 0) {\r |
d7f03464 | 610 | Status = FillTranslationTable (TranslationTable, MemoryTable);\r |
f49ea03d | 611 | if (EFI_ERROR (Status)) {\r |
4249278a | 612 | goto FreeTranslationTable;\r |
d7f03464 AB |
613 | }\r |
614 | MemoryTable++;\r | |
615 | }\r | |
616 | \r | |
4249278a AB |
617 | //\r |
618 | // EFI_MEMORY_UC ==> MAIR_ATTR_DEVICE_MEMORY\r | |
619 | // EFI_MEMORY_WC ==> MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE\r | |
620 | // EFI_MEMORY_WT ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH\r | |
621 | // EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK\r | |
622 | //\r | |
623 | ArmSetMAIR (\r | |
624 | MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |\r | |
625 | MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) |\r | |
626 | MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) |\r | |
627 | MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)\r | |
628 | );\r | |
d7f03464 AB |
629 | \r |
630 | ArmDisableAlignmentCheck ();\r | |
526f160f | 631 | ArmEnableStackAlignmentCheck ();\r |
d7f03464 AB |
632 | ArmEnableInstructionCache ();\r |
633 | ArmEnableDataCache ();\r | |
634 | \r | |
635 | ArmEnableMmu ();\r | |
f49ea03d | 636 | return EFI_SUCCESS;\r |
d7f03464 | 637 | \r |
4249278a | 638 | FreeTranslationTable:\r |
aa961dea | 639 | FreePages (TranslationTable, 1);\r |
d7f03464 AB |
640 | return Status;\r |
641 | }\r | |
642 | \r | |
643 | RETURN_STATUS\r | |
644 | EFIAPI\r | |
645 | ArmMmuBaseLibConstructor (\r | |
646 | VOID\r | |
647 | )\r | |
648 | {\r | |
649 | extern UINT32 ArmReplaceLiveTranslationEntrySize;\r | |
650 | \r | |
651 | //\r | |
652 | // The ArmReplaceLiveTranslationEntry () helper function may be invoked\r | |
653 | // with the MMU off so we have to ensure that it gets cleaned to the PoC\r | |
654 | //\r | |
655 | WriteBackDataCacheRange (ArmReplaceLiveTranslationEntry,\r | |
656 | ArmReplaceLiveTranslationEntrySize);\r | |
657 | \r | |
658 | return RETURN_SUCCESS;\r | |
659 | }\r |