UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / ArmPkg / Library / CompilerIntrinsicsLib / Arm / div.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2011, ARM. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#------------------------------------------------------------------------------\r
\r
.text\r
.align 2\r
GCC_ASM_EXPORT(__aeabi_uidiv)\r
GCC_ASM_EXPORT(__aeabi_uidivmod)\r
GCC_ASM_EXPORT(__aeabi_idiv)\r
GCC_ASM_EXPORT(__aeabi_idivmod)\r
\r
#    AREA  Math, CODE, READONLY\r
\r
#\r
#UINT32\r
#EFIAPI\r
#__aeabi_uidivmode (\r
#  IN UINT32  Dividen\r
#  IN UINT32  Divisor\r
#  );\r
#\r
\r
ASM_PFX(__aeabi_uidiv):\r
ASM_PFX(__aeabi_uidivmod):\r
  rsbs    r12, r1, r0, LSR #4\r
  mov     r2, #0\r
  bcc     ASM_PFX(__arm_div4)\r
  rsbs    r12, r1, r0, LSR #8\r
  bcc     ASM_PFX(__arm_div8)\r
  mov     r3, #0\r
  b       ASM_PFX(__arm_div_large)\r
\r
#\r
#INT32\r
#EFIAPI\r
#__aeabi_idivmode (\r
#  IN INT32  Dividen\r
#  IN INT32  Divisor\r
#  );\r
#\r
ASM_PFX(__aeabi_idiv):\r
ASM_PFX(__aeabi_idivmod):\r
  orrs    r12, r0, r1\r
  bmi     ASM_PFX(__arm_div_negative)\r
  rsbs    r12, r1, r0, LSR #1\r
  mov     r2, #0\r
  bcc     ASM_PFX(__arm_div1)\r
  rsbs    r12, r1, r0, LSR #4\r
  bcc     ASM_PFX(__arm_div4)\r
  rsbs    r12, r1, r0, LSR #8\r
  bcc     ASM_PFX(__arm_div8)\r
  mov     r3, #0\r
  b       ASM_PFX(__arm_div_large)\r
ASM_PFX(__arm_div8):\r
  rsbs    r12, r1, r0, LSR #7\r
  subcs   r0, r0, r1, LSL #7\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0,LSR #6\r
  subcs   r0, r0, r1, LSL #6\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #5\r
  subcs   r0, r0, r1, LSL #5\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #4\r
  subcs   r0, r0, r1, LSL #4\r
  adc     r2, r2, r2\r
ASM_PFX(__arm_div4):\r
  rsbs    r12, r1, r0, LSR #3\r
  subcs   r0, r0, r1, LSL #3\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #2\r
  subcs   r0, r0, r1, LSL #2\r
  adcs    r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #1\r
  subcs   r0, r0, r1, LSL #1\r
  adc     r2, r2, r2\r
ASM_PFX(__arm_div1):\r
  subs    r1, r0, r1\r
  movcc   r1, r0\r
  adc     r0, r2, r2\r
  bx      r14\r
ASM_PFX(__arm_div_negative):\r
  ands    r2, r1, #0x80000000\r
  rsbmi   r1, r1, #0\r
  eors    r3, r2, r0, ASR #32\r
  rsbcs   r0, r0, #0\r
  rsbs    r12, r1, r0, LSR #4\r
  bcc     label1\r
  rsbs    r12, r1, r0, LSR #8\r
  bcc     label2\r
ASM_PFX(__arm_div_large):\r
  lsl     r1, r1, #6\r
  rsbs    r12, r1, r0, LSR #8\r
  orr     r2, r2, #0xfc000000\r
  bcc     label2\r
  lsl     r1, r1, #6\r
  rsbs    r12, r1, r0, LSR #8\r
  orr     r2, r2, #0x3f00000\r
  bcc     label2\r
  lsl     r1, r1, #6\r
  rsbs    r12, r1, r0, LSR #8\r
  orr     r2, r2, #0xfc000\r
  orrcs   r2, r2, #0x3f00\r
  lslcs   r1, r1, #6\r
  rsbs    r12, r1, #0\r
  bcs     ASM_PFX(__aeabi_idiv0)\r
label3:\r
  lsrcs   r1, r1, #6\r
label2:\r
  rsbs    r12, r1, r0, LSR #7\r
  subcs   r0, r0, r1, LSL #7\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #6\r
  subcs   r0, r0, r1, LSL #6\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #5\r
  subcs   r0, r0, r1, LSL #5\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #4\r
  subcs   r0, r0, r1, LSL #4\r
  adc     r2, r2, r2\r
label1:\r
  rsbs    r12, r1, r0, LSR #3\r
  subcs   r0, r0, r1, LSL #3\r
  adc     r2, r2, r2\r
  rsbs    r12, r1, r0, LSR #2\r
  subcs   r0, r0, r1, LSL #2\r
  adcs    r2, r2, r2\r
  bcs     label3\r
  rsbs    r12, r1, r0, LSR #1\r
  subcs   r0, r0, r1, LSL #1\r
  adc     r2, r2, r2\r
  subs    r1, r0, r1\r
  movcc   r1, r0\r
  adc     r0, r2, r2\r
  asrs    r3, r3, #31\r
  rsbmi   r0, r0, #0\r
  rsbcs   r1, r1, #0\r
  bx      r14\r
\r
  @ What to do about division by zero?  For now, just return.\r
ASM_PFX(__aeabi_idiv0):\r
  bx      r14\r