projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3402aac7 | 1 | //------------------------------------------------------------------------------\r |
| 1e57a462 | 2 | //\r |
| 3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| e58427e3 | 4 | // Copyright (c) 2018, Pete Batard. All rights reserved.<BR>\r |
| 1e57a462 | 5 | //\r |
| 4059386c | 6 | // SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 1e57a462 | 7 | //\r |
| 8 | //------------------------------------------------------------------------------\r | |
| 9 | \r | |
| 10 | \r | |
| 11 | EXPORT __aeabi_uidiv\r | |
| 12 | EXPORT __aeabi_uidivmod\r | |
| 13 | EXPORT __aeabi_idiv\r | |
| 14 | EXPORT __aeabi_idivmod\r | |
| e58427e3 PB |
15 | EXPORT __rt_udiv\r |
| 16 | EXPORT __rt_sdiv\r | |
| 3402aac7 | 17 | \r |
| 1e57a462 | 18 | AREA Math, CODE, READONLY\r |
| 19 | \r | |
| 20 | ;\r | |
| 21 | ;UINT32\r | |
| 22 | ;EFIAPI\r | |
| e58427e3 PB |
23 | ;__aeabi_uidivmod (\r |
| 24 | ; IN UINT32 Dividend\r | |
| 1e57a462 | 25 | ; IN UINT32 Divisor\r |
| 26 | ; );\r | |
| 27 | ;\r | |
| 1e57a462 | 28 | __aeabi_uidiv\r |
| 29 | __aeabi_uidivmod\r | |
| 30 | RSBS r12, r1, r0, LSR #4\r | |
| 31 | MOV r2, #0\r | |
| 32 | BCC __arm_div4\r | |
| 33 | RSBS r12, r1, r0, LSR #8\r | |
| 34 | BCC __arm_div8\r | |
| 35 | MOV r3, #0\r | |
| 36 | B __arm_div_large\r | |
| 37 | \r | |
| e58427e3 PB |
38 | ;\r |
| 39 | ;UINT64\r | |
| 40 | ;EFIAPI\r | |
| 41 | ;__rt_udiv (\r | |
| 42 | ; IN UINT32 Divisor,\r | |
| 43 | ; IN UINT32 Dividend\r | |
| 44 | ; );\r | |
| 45 | ;\r | |
| 46 | __rt_udiv\r | |
| 47 | ; Swap R0 and R1\r | |
| 48 | MOV r12, r0\r | |
| 49 | MOV r0, r1\r | |
| 50 | MOV r1, r12\r | |
| 51 | B __aeabi_uidivmod\r | |
| 52 | \r | |
| 53 | ;\r | |
| 54 | ;UINT64\r | |
| 55 | ;EFIAPI\r | |
| 56 | ;__rt_sdiv (\r | |
| 57 | ; IN INT32 Divisor,\r | |
| 58 | ; IN INT32 Dividend\r | |
| 59 | ; );\r | |
| 60 | ;\r | |
| 61 | __rt_sdiv\r | |
| 62 | ; Swap R0 and R1\r | |
| 63 | MOV r12, r0\r | |
| 64 | MOV r0, r1\r | |
| 65 | MOV r1, r12\r | |
| 66 | B __aeabi_idivmod\r | |
| 67 | \r | |
| 1e57a462 | 68 | ;\r |
| 69 | ;INT32\r | |
| 70 | ;EFIAPI\r | |
| e58427e3 PB |
71 | ;__aeabi_idivmod (\r |
| 72 | ; IN INT32 Dividend\r | |
| 1e57a462 | 73 | ; IN INT32 Divisor\r |
| 74 | ; );\r | |
| 75 | ;\r | |
| 76 | __aeabi_idiv\r | |
| 77 | __aeabi_idivmod\r | |
| 78 | ORRS r12, r0, r1\r | |
| 79 | BMI __arm_div_negative\r | |
| 80 | RSBS r12, r1, r0, LSR #1\r | |
| 81 | MOV r2, #0\r | |
| 82 | BCC __arm_div1\r | |
| 83 | RSBS r12, r1, r0, LSR #4\r | |
| 84 | BCC __arm_div4\r | |
| 85 | RSBS r12, r1, r0, LSR #8\r | |
| 86 | BCC __arm_div8\r | |
| 87 | MOV r3, #0\r | |
| 88 | B __arm_div_large\r | |
| 89 | __arm_div8\r | |
| 90 | RSBS r12, r1, r0, LSR #7\r | |
| 91 | SUBCS r0, r0, r1, LSL #7\r | |
| 92 | ADC r2, r2, r2\r | |
| 93 | RSBS r12, r1, r0,LSR #6\r | |
| 94 | SUBCS r0, r0, r1, LSL #6\r | |
| 95 | ADC r2, r2, r2\r | |
| 96 | RSBS r12, r1, r0, LSR #5\r | |
| 97 | SUBCS r0, r0, r1, LSL #5\r | |
| 98 | ADC r2, r2, r2\r | |
| 99 | RSBS r12, r1, r0, LSR #4\r | |
| 100 | SUBCS r0, r0, r1, LSL #4\r | |
| 101 | ADC r2, r2, r2\r | |
| 102 | __arm_div4\r | |
| 103 | RSBS r12, r1, r0, LSR #3\r | |
| 104 | SUBCS r0, r0, r1, LSL #3\r | |
| 105 | ADC r2, r2, r2\r | |
| 106 | RSBS r12, r1, r0, LSR #2\r | |
| 107 | SUBCS r0, r0, r1, LSL #2\r | |
| 108 | ADCS r2, r2, r2\r | |
| 109 | RSBS r12, r1, r0, LSR #1\r | |
| 110 | SUBCS r0, r0, r1, LSL #1\r | |
| 111 | ADC r2, r2, r2\r | |
| 112 | __arm_div1\r | |
| 113 | SUBS r1, r0, r1\r | |
| 114 | MOVCC r1, r0\r | |
| 115 | ADC r0, r2, r2\r | |
| 116 | BX r14\r | |
| 117 | __arm_div_negative\r | |
| 118 | ANDS r2, r1, #0x80000000\r | |
| 119 | RSBMI r1, r1, #0\r | |
| 120 | EORS r3, r2, r0, ASR #32\r | |
| 121 | RSBCS r0, r0, #0\r | |
| 122 | RSBS r12, r1, r0, LSR #4\r | |
| 123 | BCC label1\r | |
| 124 | RSBS r12, r1, r0, LSR #8\r | |
| 125 | BCC label2\r | |
| 126 | __arm_div_large\r | |
| 127 | LSL r1, r1, #6\r | |
| 128 | RSBS r12, r1, r0, LSR #8\r | |
| 129 | ORR r2, r2, #0xfc000000\r | |
| 130 | BCC label2\r | |
| 131 | LSL r1, r1, #6\r | |
| 132 | RSBS r12, r1, r0, LSR #8\r | |
| 133 | ORR r2, r2, #0x3f00000\r | |
| 134 | BCC label2\r | |
| 135 | LSL r1, r1, #6\r | |
| 136 | RSBS r12, r1, r0, LSR #8\r | |
| 137 | ORR r2, r2, #0xfc000\r | |
| 138 | ORRCS r2, r2, #0x3f00\r | |
| 139 | LSLCS r1, r1, #6\r | |
| 140 | RSBS r12, r1, #0\r | |
| 141 | BCS __aeabi_idiv0\r | |
| 142 | label3\r | |
| 143 | LSRCS r1, r1, #6\r | |
| 144 | label2\r | |
| 145 | RSBS r12, r1, r0, LSR #7\r | |
| 146 | SUBCS r0, r0, r1, LSL #7\r | |
| 147 | ADC r2, r2, r2\r | |
| 148 | RSBS r12, r1, r0, LSR #6\r | |
| 149 | SUBCS r0, r0, r1, LSL #6\r | |
| 150 | ADC r2, r2, r2\r | |
| 151 | RSBS r12, r1, r0, LSR #5\r | |
| 152 | SUBCS r0, r0, r1, LSL #5\r | |
| 153 | ADC r2, r2, r2\r | |
| 154 | RSBS r12, r1, r0, LSR #4\r | |
| 155 | SUBCS r0, r0, r1, LSL #4\r | |
| 156 | ADC r2, r2, r2\r | |
| 157 | label1\r | |
| 158 | RSBS r12, r1, r0, LSR #3\r | |
| 159 | SUBCS r0, r0, r1, LSL #3\r | |
| 160 | ADC r2, r2, r2\r | |
| 161 | RSBS r12, r1, r0, LSR #2\r | |
| 162 | SUBCS r0, r0, r1, LSL #2\r | |
| 163 | ADCS r2, r2, r2\r | |
| 164 | BCS label3\r | |
| 165 | RSBS r12, r1, r0, LSR #1\r | |
| 166 | SUBCS r0, r0, r1, LSL #1\r | |
| 167 | ADC r2, r2, r2\r | |
| 168 | SUBS r1, r0, r1\r | |
| 169 | MOVCC r1, r0\r | |
| 170 | ADC r0, r2, r2\r | |
| 171 | ASRS r3, r3, #31\r | |
| 172 | RSBMI r0, r0, #0\r | |
| 173 | RSBCS r1, r1, #0\r | |
| 174 | BX r14\r | |
| 175 | \r | |
| 176 | ; What to do about division by zero? For now, just return.\r | |
| 177 | __aeabi_idiv0\r | |
| 178 | BX r14\r | |
| 3402aac7 | 179 | \r |
| 1e57a462 | 180 | END\r |